RTS: fix xchg/cas fcns to invoke memory barrier on ARMv7 platform
authorKarel Gardas <karel.gardas@centrum.cz>
Sat, 9 Jul 2011 15:54:30 +0000 (17:54 +0200)
committerManuel M T Chakravarty <chak@cse.unsw.edu.au>
Wed, 10 Aug 2011 12:03:41 +0000 (22:03 +1000)
This patch fixes RTS' xchg and cas functions. On ARMv7 it is recommended
to add memory barrier after using ldrex/strex for implementing atomic
lock or operation.

includes/stg/SMP.h

index df62e56..4162058 100644 (file)
@@ -156,6 +156,9 @@ xchg(StgPtr p, StgWord w)
                           "      strex  %1, %2, [%3]\n"
                           "      teq    %1, #1\n"
                           "      beq    1b\n"
+#if !defined(PRE_ARMv7)
+                          "      dmb\n"
+#endif
                           : "=&r" (result), "=&r" (tmp)
                           : "r" (w), "r" (p)
                           : "memory"
@@ -225,6 +228,9 @@ cas(StgVolatilePtr p, StgWord o, StgWord n)
         "       teq     %0, #1\n"
         "       it      eq\n"
         "       beq     1b\n"
+#if !defined(PRE_ARMv7)
+        "       dmb\n"
+#endif
                 : "=&r"(tmp), "=&r"(result)
                 : "r"(p), "r"(o), "r"(n)
                 : "cc","memory");