RTS: Add missing memory barrier
authorPeter Trommler <ptrommler@acm.org>
Sun, 24 Feb 2019 16:11:00 +0000 (17:11 +0100)
committerMarge Bot <ben+marge-bot@smart-cactus.org>
Wed, 27 Feb 2019 14:59:59 +0000 (09:59 -0500)
commit5c084e0468be46f5ab48b2c1669a7e4d4d0f3c43
tree148d5b9dcae8f5f3701bc05a0a0d89386a33a1d7
parent5bc195b1fe788e9a900a15fbe473967850517c3e
RTS: Add missing memory barrier

In the work stealing queue a load-load-barrier is required to ensure
that a read of queue data cannot be reordered before a read of the
bottom pointer into the queue.

The added load-load-barrier ensures that the ordering of writes enforced
at the end of `pushWSDeque` is also respected in the order of reads in
`stealWSDeque_`. In other words, when reading `q->bottom` we want to make
sure that we see the updates to `q->elements`.

Fixes #13633
rts/WSDeque.c
testsuite/tests/rts/testwsdeque.c