Fix for T14251 on ARM
authorKavon Farvardin <kavon@farvard.in>
Sun, 28 Oct 2018 16:11:49 +0000 (12:11 -0400)
committerBen Gamari <ben@smart-cactus.org>
Sun, 28 Oct 2018 17:32:30 +0000 (13:32 -0400)
commit2e23e1c7de01c92b038e55ce53d11bf9db993dd4
tree089bc437dce1628c38e611b93c5fa278a72b4fe1
parent093bbff2ce85709117280c9ec7855b1f201d894f
Fix for T14251 on ARM

We now calculate the SSE register padding needed to fix the calling
convention in LLVM in a robust way: grouping them by whether
registers in that class overlap (with the same class overlapping
itself).

My prior patch assumed that no matter the platform, physical
register Fx aliases with Dx, etc, for our calling convention.

This is unfortunately not the case for any platform except x86-64.

Test Plan:
Only know how to test on x86-64, but it should be tested on ARM with:

`make test WAYS=llvm && make test WAYS=optllvm`

Reviewers: bgamari, angerman

Reviewed By: bgamari

Subscribers: rwbarton, carter

GHC Trac Issues: #15780, #14251, #15747

Differential Revision: https://phabricator.haskell.org/D5254

(cherry picked from commit c36a2b596a6ba9d7a0a80df01b3c041720c727ca)
compiler/llvmGen/LlvmCodeGen/Base.hs
compiler/llvmGen/LlvmCodeGen/CodeGen.hs