llvmGen: Pass vector arguments in vector registers by default
authorBen Gamari <bgamari.foss@gmail.com>
Thu, 2 Nov 2017 21:28:40 +0000 (17:28 -0400)
committerBen Gamari <ben@smart-cactus.org>
Fri, 3 Nov 2017 00:15:47 +0000 (20:15 -0400)
commit15f788f5e5096641245a4f060600a6db9cbc2c4e
tree99fa80ab340ffc5860eb5abef778c54d68da3e22
parent43537568579a63cb6b8d70b4815d76c46bb9a692
llvmGen: Pass vector arguments in vector registers by default

Earlier this year Edward Kmett requested [1] that we enable passing of
vector values in vector registers by default. The GHC calling convention
changes have been in LLVM for a number of years now so let's just flip
the switch.

[1] https://mail.haskell.org/pipermail/ghc-devs/2017-March/013905.html

Reviewers: austin

Subscribers: rwbarton, thomie

Differential Revision: https://phabricator.haskell.org/D4142
compiler/main/DynFlags.hs
docs/users_guide/using-optimisation.rst