f58e49e626e49b0efa24d5ebfcef542086451c6f
[ghc.git] / includes / stg / MachRegs.h
1 /* -----------------------------------------------------------------------------
2 *
3 * (c) The GHC Team, 1998-2014
4 *
5 * Registers used in STG code. Might or might not correspond to
6 * actual machine registers.
7 *
8 * Do not #include this file directly: #include "Rts.h" instead.
9 *
10 * To understand the structure of the RTS headers, see the wiki:
11 * http://ghc.haskell.org/trac/ghc/wiki/Commentary/SourceTree/Includes
12 *
13 * ---------------------------------------------------------------------------*/
14
15 #pragma once
16
17 /* This file is #included into Haskell code in the compiler: #defines
18 * only in here please.
19 */
20
21 /*
22 * Undefine these as a precaution: some of them were found to be
23 * defined by system headers on ARM/Linux.
24 */
25 #undef REG_R1
26 #undef REG_R2
27 #undef REG_R3
28 #undef REG_R4
29 #undef REG_R5
30 #undef REG_R6
31 #undef REG_R7
32 #undef REG_R8
33 #undef REG_R9
34 #undef REG_R10
35
36 /*
37 * Defining MACHREGS_NO_REGS to 1 causes no global registers to be used.
38 * MACHREGS_NO_REGS is typically controlled by NO_REGS, which is
39 * typically defined by GHC, via a command-line option passed to gcc,
40 * when the -funregisterised flag is given.
41 *
42 * NB. When MACHREGS_NO_REGS to 1, calling & return conventions may be
43 * different. For example, all function arguments will be passed on
44 * the stack, and components of an unboxed tuple will be returned on
45 * the stack rather than in registers.
46 */
47 #if MACHREGS_NO_REGS == 1
48
49 /* Nothing */
50
51 #elif MACHREGS_NO_REGS == 0
52
53 /* ----------------------------------------------------------------------------
54 Caller saves and callee-saves regs.
55
56 Caller-saves regs have to be saved around C-calls made from STG
57 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
58 is designated caller-saves in that machine's C calling convention.
59
60 As it stands, the only registers that are ever marked caller saves
61 are the RX, FX, DX and USER registers; as a result, if you
62 decide to caller save a system register (e.g. SP, HP, etc), note that
63 this code path is completely untested! -- EZY
64 -------------------------------------------------------------------------- */
65
66 /* -----------------------------------------------------------------------------
67 The x86 register mapping
68
69 Ok, we've only got 6 general purpose registers, a frame pointer and a
70 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
71 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
72 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
73
74 Reg STG-Reg
75 ---------------
76 ebx Base
77 ebp Sp
78 esi R1
79 edi Hp
80
81 Leaving SpLim out of the picture.
82 -------------------------------------------------------------------------- */
83
84 #ifdef MACHREGS_i386
85
86 #define REG(x) __asm__("%" #x)
87
88 #ifndef not_doing_dynamic_linking
89 #define REG_Base ebx
90 #endif
91 #define REG_Sp ebp
92
93 #ifndef STOLEN_X86_REGS
94 #define STOLEN_X86_REGS 4
95 #endif
96
97 #if STOLEN_X86_REGS >= 3
98 # define REG_R1 esi
99 #endif
100
101 #if STOLEN_X86_REGS >= 4
102 # define REG_Hp edi
103 #endif
104 #define REG_MachSp esp
105
106 #define REG_XMM1 xmm0
107 #define REG_XMM2 xmm1
108 #define REG_XMM3 xmm2
109 #define REG_XMM4 xmm3
110
111 #define REG_YMM1 ymm0
112 #define REG_YMM2 ymm1
113 #define REG_YMM3 ymm2
114 #define REG_YMM4 ymm3
115
116 #define REG_ZMM1 zmm0
117 #define REG_ZMM2 zmm1
118 #define REG_ZMM3 zmm2
119 #define REG_ZMM4 zmm3
120
121 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
122 #define MAX_REAL_FLOAT_REG 0
123 #define MAX_REAL_DOUBLE_REG 0
124 #define MAX_REAL_LONG_REG 0
125 #define MAX_REAL_XMM_REG 4
126 #define MAX_REAL_YMM_REG 4
127 #define MAX_REAL_ZMM_REG 4
128
129 /* -----------------------------------------------------------------------------
130 The x86-64 register mapping
131
132 %rax caller-saves, don't steal this one
133 %rbx YES
134 %rcx arg reg, caller-saves
135 %rdx arg reg, caller-saves
136 %rsi arg reg, caller-saves
137 %rdi arg reg, caller-saves
138 %rbp YES (our *prime* register)
139 %rsp (unavailable - stack pointer)
140 %r8 arg reg, caller-saves
141 %r9 arg reg, caller-saves
142 %r10 caller-saves
143 %r11 caller-saves
144 %r12 YES
145 %r13 YES
146 %r14 YES
147 %r15 YES
148
149 %xmm0-7 arg regs, caller-saves
150 %xmm8-15 caller-saves
151
152 Use the caller-saves regs for Rn, because we don't always have to
153 save those (as opposed to Sp/Hp/SpLim etc. which always have to be
154 saved).
155
156 --------------------------------------------------------------------------- */
157
158 #elif defined(MACHREGS_x86_64)
159
160 #define REG(x) __asm__("%" #x)
161
162 #define REG_Base r13
163 #define REG_Sp rbp
164 #define REG_Hp r12
165 #define REG_R1 rbx
166 #define REG_R2 r14
167 #define REG_R3 rsi
168 #define REG_R4 rdi
169 #define REG_R5 r8
170 #define REG_R6 r9
171 #define REG_SpLim r15
172 #define REG_MachSp rsp
173
174 /*
175 Map both Fn and Dn to register xmmn so that we can pass a function any
176 combination of up to six Float# or Double# arguments without touching
177 the stack. See Note [Overlapping global registers] for implications.
178 */
179
180 #define REG_F1 xmm1
181 #define REG_F2 xmm2
182 #define REG_F3 xmm3
183 #define REG_F4 xmm4
184 #define REG_F5 xmm5
185 #define REG_F6 xmm6
186
187 #define REG_D1 xmm1
188 #define REG_D2 xmm2
189 #define REG_D3 xmm3
190 #define REG_D4 xmm4
191 #define REG_D5 xmm5
192 #define REG_D6 xmm6
193
194 #define REG_XMM1 xmm1
195 #define REG_XMM2 xmm2
196 #define REG_XMM3 xmm3
197 #define REG_XMM4 xmm4
198 #define REG_XMM5 xmm5
199 #define REG_XMM6 xmm6
200
201 #define REG_YMM1 ymm1
202 #define REG_YMM2 ymm2
203 #define REG_YMM3 ymm3
204 #define REG_YMM4 ymm4
205 #define REG_YMM5 ymm5
206 #define REG_YMM6 ymm6
207
208 #define REG_ZMM1 zmm1
209 #define REG_ZMM2 zmm2
210 #define REG_ZMM3 zmm3
211 #define REG_ZMM4 zmm4
212 #define REG_ZMM5 zmm5
213 #define REG_ZMM6 zmm6
214
215 #if !defined(mingw32_HOST_OS)
216 #define CALLER_SAVES_R3
217 #define CALLER_SAVES_R4
218 #endif
219 #define CALLER_SAVES_R5
220 #define CALLER_SAVES_R6
221
222 #define CALLER_SAVES_F1
223 #define CALLER_SAVES_F2
224 #define CALLER_SAVES_F3
225 #define CALLER_SAVES_F4
226 #define CALLER_SAVES_F5
227 #if !defined(mingw32_HOST_OS)
228 #define CALLER_SAVES_F6
229 #endif
230
231 #define CALLER_SAVES_D1
232 #define CALLER_SAVES_D2
233 #define CALLER_SAVES_D3
234 #define CALLER_SAVES_D4
235 #define CALLER_SAVES_D5
236 #if !defined(mingw32_HOST_OS)
237 #define CALLER_SAVES_D6
238 #endif
239
240 #define CALLER_SAVES_XMM1
241 #define CALLER_SAVES_XMM2
242 #define CALLER_SAVES_XMM3
243 #define CALLER_SAVES_XMM4
244 #define CALLER_SAVES_XMM5
245 #if !defined(mingw32_HOST_OS)
246 #define CALLER_SAVES_XMM6
247 #endif
248
249 #define CALLER_SAVES_YMM1
250 #define CALLER_SAVES_YMM2
251 #define CALLER_SAVES_YMM3
252 #define CALLER_SAVES_YMM4
253 #define CALLER_SAVES_YMM5
254 #if !defined(mingw32_HOST_OS)
255 #define CALLER_SAVES_YMM6
256 #endif
257
258 #define CALLER_SAVES_ZMM1
259 #define CALLER_SAVES_ZMM2
260 #define CALLER_SAVES_ZMM3
261 #define CALLER_SAVES_ZMM4
262 #define CALLER_SAVES_ZMM5
263 #if !defined(mingw32_HOST_OS)
264 #define CALLER_SAVES_ZMM6
265 #endif
266
267 #define MAX_REAL_VANILLA_REG 6
268 #define MAX_REAL_FLOAT_REG 6
269 #define MAX_REAL_DOUBLE_REG 6
270 #define MAX_REAL_LONG_REG 0
271 #define MAX_REAL_XMM_REG 6
272 #define MAX_REAL_YMM_REG 6
273 #define MAX_REAL_ZMM_REG 6
274
275 /* -----------------------------------------------------------------------------
276 The PowerPC register mapping
277
278 0 system glue? (caller-save, volatile)
279 1 SP (callee-save, non-volatile)
280 2 AIX, powerpc64-linux:
281 RTOC (a strange special case)
282 darwin:
283 (caller-save, volatile)
284 powerpc32-linux:
285 reserved for use by system
286
287 3-10 args/return (caller-save, volatile)
288 11,12 system glue? (caller-save, volatile)
289 13 on 64-bit: reserved for thread state pointer
290 on 32-bit: (callee-save, non-volatile)
291 14-31 (callee-save, non-volatile)
292
293 f0 (caller-save, volatile)
294 f1-f13 args/return (caller-save, volatile)
295 f14-f31 (callee-save, non-volatile)
296
297 \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes.
298 \tr{0}--\tr{12} are caller-save registers.
299
300 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
301
302 We can do the Whole Business with callee-save registers only!
303 -------------------------------------------------------------------------- */
304
305 #elif defined(MACHREGS_powerpc)
306
307 #define REG(x) __asm__(#x)
308
309 #define REG_R1 r14
310 #define REG_R2 r15
311 #define REG_R3 r16
312 #define REG_R4 r17
313 #define REG_R5 r18
314 #define REG_R6 r19
315 #define REG_R7 r20
316 #define REG_R8 r21
317
318 #ifdef MACHREGS_darwin
319
320 #define REG_F1 f14
321 #define REG_F2 f15
322 #define REG_F3 f16
323 #define REG_F4 f17
324
325 #define REG_D1 f18
326 #define REG_D2 f19
327
328 #else
329
330 #define REG_F1 fr14
331 #define REG_F2 fr15
332 #define REG_F3 fr16
333 #define REG_F4 fr17
334 #define REG_F5 fr18
335 #define REG_F6 fr19
336
337 #define REG_D1 fr20
338 #define REG_D2 fr21
339 #define REG_D3 fr22
340 #define REG_D4 fr23
341 #define REG_D5 fr24
342 #define REG_D6 fr25
343
344 #endif
345
346 #define REG_Sp r22
347 #define REG_SpLim r24
348
349 #define REG_Hp r25
350
351 #define REG_Base r27
352
353 /* -----------------------------------------------------------------------------
354 The Sun SPARC register mapping
355
356 !! IMPORTANT: if you change this register mapping you must also update
357 compiler/nativeGen/SPARC/Regs.hs. That file handles the
358 mapping for the NCG. This one only affects via-c code.
359
360 The SPARC register (window) story: Remember, within the Haskell
361 Threaded World, we essentially ``shut down'' the register-window
362 mechanism---the window doesn't move at all while in this World. It
363 *does* move, of course, if we call out to arbitrary~C...
364
365 The %i, %l, and %o registers (8 each) are the input, local, and
366 output registers visible in one register window. The 8 %g (global)
367 registers are visible all the time.
368
369 zero: always zero
370 scratch: volatile across C-fn calls. used by linker.
371 app: usable by application
372 system: reserved for system
373
374 alloc: allocated to in the register allocator, intra-closure only
375
376 GHC usage v8 ABI v9 ABI
377 Global
378 %g0 zero zero zero
379 %g1 alloc scratch scrach
380 %g2 alloc app app
381 %g3 alloc app app
382 %g4 alloc app scratch
383 %g5 system scratch
384 %g6 system system
385 %g7 system system
386
387 Output: can be zapped by callee
388 %o0-o5 alloc caller saves
389 %o6 C stack ptr
390 %o7 C ret addr
391
392 Local: maintained by register windowing mechanism
393 %l0 alloc
394 %l1 R1
395 %l2 R2
396 %l3 R3
397 %l4 R4
398 %l5 R5
399 %l6 alloc
400 %l7 alloc
401
402 Input
403 %i0 Sp
404 %i1 Base
405 %i2 SpLim
406 %i3 Hp
407 %i4 alloc
408 %i5 R6
409 %i6 C frame ptr
410 %i7 C ret addr
411
412 The paired nature of the floating point registers causes complications for
413 the native code generator. For convenience, we pretend that the first 22
414 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
415 float (single) regs. The NCG acts accordingly. That means that the
416 following FP assignment is rather fragile, and should only be changed
417 with extreme care. The current scheme is:
418
419 %f0 /%f1 FP return from C
420 %f2 /%f3 D1
421 %f4 /%f5 D2
422 %f6 /%f7 ncg double spill tmp #1
423 %f8 /%f9 ncg double spill tmp #2
424 %f10/%f11 allocatable
425 %f12/%f13 allocatable
426 %f14/%f15 allocatable
427 %f16/%f17 allocatable
428 %f18/%f19 allocatable
429 %f20/%f21 allocatable
430
431 %f22 F1
432 %f23 F2
433 %f24 F3
434 %f25 F4
435 %f26 ncg single spill tmp #1
436 %f27 ncg single spill tmp #2
437 %f28 allocatable
438 %f29 allocatable
439 %f30 allocatable
440 %f31 allocatable
441
442 -------------------------------------------------------------------------- */
443
444 #elif defined(MACHREGS_sparc)
445
446 #define REG(x) __asm__("%" #x)
447
448 #define CALLER_SAVES_USER
449
450 #define CALLER_SAVES_F1
451 #define CALLER_SAVES_F2
452 #define CALLER_SAVES_F3
453 #define CALLER_SAVES_F4
454 #define CALLER_SAVES_D1
455 #define CALLER_SAVES_D2
456
457 #define REG_R1 l1
458 #define REG_R2 l2
459 #define REG_R3 l3
460 #define REG_R4 l4
461 #define REG_R5 l5
462 #define REG_R6 i5
463
464 #define REG_F1 f22
465 #define REG_F2 f23
466 #define REG_F3 f24
467 #define REG_F4 f25
468
469 /* for each of the double arg regs,
470 Dn_2 is the high half. */
471
472 #define REG_D1 f2
473 #define REG_D1_2 f3
474
475 #define REG_D2 f4
476 #define REG_D2_2 f5
477
478 #define REG_Sp i0
479 #define REG_SpLim i2
480
481 #define REG_Hp i3
482
483 #define REG_Base i1
484
485 #define NCG_FirstFloatReg f22
486
487 /* -----------------------------------------------------------------------------
488 The ARM EABI register mapping
489
490 Here we consider ARM mode (i.e. 32bit isns)
491 and also CPU with full VFPv3 implementation
492
493 ARM registers (see Chapter 5.1 in ARM IHI 0042D and
494 Section 9.2.2 in ARM Software Development Toolkit Reference Guide)
495
496 r15 PC The Program Counter.
497 r14 LR The Link Register.
498 r13 SP The Stack Pointer.
499 r12 IP The Intra-Procedure-call scratch register.
500 r11 v8/fp Variable-register 8.
501 r10 v7/sl Variable-register 7.
502 r9 v6/SB/TR Platform register. The meaning of this register is
503 defined by the platform standard.
504 r8 v5 Variable-register 5.
505 r7 v4 Variable register 4.
506 r6 v3 Variable register 3.
507 r5 v2 Variable register 2.
508 r4 v1 Variable register 1.
509 r3 a4 Argument / scratch register 4.
510 r2 a3 Argument / scratch register 3.
511 r1 a2 Argument / result / scratch register 2.
512 r0 a1 Argument / result / scratch register 1.
513
514 VFPv2/VFPv3/NEON registers
515 s0-s15/d0-d7/q0-q3 Argument / result/ scratch registers
516 s16-s31/d8-d15/q4-q7 callee-saved registers (must be preserved across
517 subroutine calls)
518
519 VFPv3/NEON registers (added to the VFPv2 registers set)
520 d16-d31/q8-q15 Argument / result/ scratch registers
521 ----------------------------------------------------------------------------- */
522
523 #elif defined(MACHREGS_arm)
524
525 #define REG(x) __asm__(#x)
526
527 #define REG_Base r4
528 #define REG_Sp r5
529 #define REG_Hp r6
530 #define REG_R1 r7
531 #define REG_R2 r8
532 #define REG_R3 r9
533 #define REG_R4 r10
534 #define REG_SpLim r11
535
536 #if !defined(arm_HOST_ARCH_PRE_ARMv6)
537 /* d8 */
538 #define REG_F1 s16
539 #define REG_F2 s17
540 /* d9 */
541 #define REG_F3 s18
542 #define REG_F4 s19
543
544 #define REG_D1 d10
545 #define REG_D2 d11
546 #endif
547
548 /* -----------------------------------------------------------------------------
549 The ARMv8/AArch64 ABI register mapping
550
551 The AArch64 provides 31 64-bit general purpose registers
552 and 32 128-bit SIMD/floating point registers.
553
554 General purpose registers (see Chapter 5.1.1 in ARM IHI 0055B)
555
556 Register | Special | Role in the procedure call standard
557 ---------+---------+------------------------------------
558 SP | | The Stack Pointer
559 r30 | LR | The Link Register
560 r29 | FP | The Frame Pointer
561 r19-r28 | | Callee-saved registers
562 r18 | | The Platform Register, if needed;
563 | | or temporary register
564 r17 | IP1 | The second intra-procedure-call temporary register
565 r16 | IP0 | The first intra-procedure-call scratch register
566 r9-r15 | | Temporary registers
567 r8 | | Indirect result location register
568 r0-r7 | | Parameter/result registers
569
570
571 FPU/SIMD registers
572
573 s/d/q/v0-v7 Argument / result/ scratch registers
574 s/d/q/v8-v15 callee-saved registers (must be preserved across subroutine calls,
575 but only bottom 64-bit value needs to be preserved)
576 s/d/q/v16-v31 temporary registers
577
578 ----------------------------------------------------------------------------- */
579
580 #elif defined(MACHREGS_aarch64)
581
582 #define REG(x) __asm__(#x)
583
584 #define REG_Base r19
585 #define REG_Sp r20
586 #define REG_Hp r21
587 #define REG_R1 r22
588 #define REG_R2 r23
589 #define REG_R3 r24
590 #define REG_R4 r25
591 #define REG_R5 r26
592 #define REG_R6 r27
593 #define REG_SpLim r28
594
595 #define REG_F1 s8
596 #define REG_F2 s9
597 #define REG_F3 s10
598 #define REG_F4 s11
599
600 #define REG_D1 d12
601 #define REG_D2 d13
602 #define REG_D3 d14
603 #define REG_D4 d15
604
605 #else
606
607 #error Cannot find platform to give register info for
608
609 #endif
610
611 #else
612
613 #error Bad MACHREGS_NO_REGS value
614
615 #endif
616
617 /* -----------------------------------------------------------------------------
618 * These constants define how many stg registers will be used for
619 * passing arguments (and results, in the case of an unboxed-tuple
620 * return).
621 *
622 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
623 * highest STG register to occupy a real machine register, otherwise
624 * the calling conventions will needlessly shuffle data between the
625 * stack and memory-resident STG registers. We might occasionally
626 * set these macros to other values for testing, though.
627 *
628 * Registers above these values might still be used, for instance to
629 * communicate with PrimOps and RTS functions.
630 */
631
632 #ifndef MAX_REAL_VANILLA_REG
633 # if defined(REG_R10)
634 # define MAX_REAL_VANILLA_REG 10
635 # elif defined(REG_R9)
636 # define MAX_REAL_VANILLA_REG 9
637 # elif defined(REG_R8)
638 # define MAX_REAL_VANILLA_REG 8
639 # elif defined(REG_R7)
640 # define MAX_REAL_VANILLA_REG 7
641 # elif defined(REG_R6)
642 # define MAX_REAL_VANILLA_REG 6
643 # elif defined(REG_R5)
644 # define MAX_REAL_VANILLA_REG 5
645 # elif defined(REG_R4)
646 # define MAX_REAL_VANILLA_REG 4
647 # elif defined(REG_R3)
648 # define MAX_REAL_VANILLA_REG 3
649 # elif defined(REG_R2)
650 # define MAX_REAL_VANILLA_REG 2
651 # elif defined(REG_R1)
652 # define MAX_REAL_VANILLA_REG 1
653 # else
654 # define MAX_REAL_VANILLA_REG 0
655 # endif
656 #endif
657
658 #ifndef MAX_REAL_FLOAT_REG
659 # if defined(REG_F4)
660 # define MAX_REAL_FLOAT_REG 4
661 # elif defined(REG_F3)
662 # define MAX_REAL_FLOAT_REG 3
663 # elif defined(REG_F2)
664 # define MAX_REAL_FLOAT_REG 2
665 # elif defined(REG_F1)
666 # define MAX_REAL_FLOAT_REG 1
667 # else
668 # define MAX_REAL_FLOAT_REG 0
669 # endif
670 #endif
671
672 #ifndef MAX_REAL_DOUBLE_REG
673 # if defined(REG_D2)
674 # define MAX_REAL_DOUBLE_REG 2
675 # elif defined(REG_D1)
676 # define MAX_REAL_DOUBLE_REG 1
677 # else
678 # define MAX_REAL_DOUBLE_REG 0
679 # endif
680 #endif
681
682 #ifndef MAX_REAL_LONG_REG
683 # if defined(REG_L1)
684 # define MAX_REAL_LONG_REG 1
685 # else
686 # define MAX_REAL_LONG_REG 0
687 # endif
688 #endif
689
690 #ifndef MAX_REAL_XMM_REG
691 # if defined(REG_XMM6)
692 # define MAX_REAL_XMM_REG 6
693 # elif defined(REG_XMM5)
694 # define MAX_REAL_XMM_REG 5
695 # elif defined(REG_XMM4)
696 # define MAX_REAL_XMM_REG 4
697 # elif defined(REG_XMM3)
698 # define MAX_REAL_XMM_REG 3
699 # elif defined(REG_XMM2)
700 # define MAX_REAL_XMM_REG 2
701 # elif defined(REG_XMM1)
702 # define MAX_REAL_XMM_REG 1
703 # else
704 # define MAX_REAL_XMM_REG 0
705 # endif
706 #endif
707
708 /* define NO_ARG_REGS if we have no argument registers at all (we can
709 * optimise certain code paths using this predicate).
710 */
711 #if MAX_REAL_VANILLA_REG < 2
712 #define NO_ARG_REGS
713 #else
714 #undef NO_ARG_REGS
715 #endif