Draw STG F and D registers from the same pool of available SSE registers on x86-64.
[ghc.git] / includes / CodeGen.Platform.hs
1
2 import CmmExpr
3 import FastBool
4 #if !(MACHREGS_i386 || MACHREGS_x86_64 || MACHREGS_sparc || MACHREGS_powerpc)
5 import Panic
6 #endif
7 import Reg
8
9 #include "stg/MachRegs.h"
10
11 #if MACHREGS_i386 || MACHREGS_x86_64
12
13 # if MACHREGS_i386
14 # define eax 0
15 # define ebx 1
16 # define ecx 2
17 # define edx 3
18 # define esi 4
19 # define edi 5
20 # define ebp 6
21 # define esp 7
22 # endif
23
24 # if MACHREGS_x86_64
25 # define rax 0
26 # define rbx 1
27 # define rcx 2
28 # define rdx 3
29 # define rsi 4
30 # define rdi 5
31 # define rbp 6
32 # define rsp 7
33 # define r8 8
34 # define r9 9
35 # define r10 10
36 # define r11 11
37 # define r12 12
38 # define r13 13
39 # define r14 14
40 # define r15 15
41 # endif
42
43 # define fake0 16
44 # define fake1 17
45 # define fake2 18
46 # define fake3 19
47 # define fake4 20
48 # define fake5 21
49
50 # define xmm0 24
51 # define xmm1 25
52 # define xmm2 26
53 # define xmm3 27
54 # define xmm4 28
55 # define xmm5 29
56 # define xmm6 30
57 # define xmm7 31
58 # define xmm8 32
59 # define xmm9 33
60 # define xmm10 34
61 # define xmm11 35
62 # define xmm12 36
63 # define xmm13 37
64 # define xmm14 38
65 # define xmm15 39
66
67 #elif MACHREGS_powerpc
68
69 # define r0 0
70 # define r1 1
71 # define r2 2
72 # define r3 3
73 # define r4 4
74 # define r5 5
75 # define r6 6
76 # define r7 7
77 # define r8 8
78 # define r9 9
79 # define r10 10
80 # define r11 11
81 # define r12 12
82 # define r13 13
83 # define r14 14
84 # define r15 15
85 # define r16 16
86 # define r17 17
87 # define r18 18
88 # define r19 19
89 # define r20 20
90 # define r21 21
91 # define r22 22
92 # define r23 23
93 # define r24 24
94 # define r25 25
95 # define r26 26
96 # define r27 27
97 # define r28 28
98 # define r29 29
99 # define r30 30
100 # define r31 31
101
102 # if MACHREGS_darwin
103 # define f0 32
104 # define f1 33
105 # define f2 34
106 # define f3 35
107 # define f4 36
108 # define f5 37
109 # define f6 38
110 # define f7 39
111 # define f8 40
112 # define f9 41
113 # define f10 42
114 # define f11 43
115 # define f12 44
116 # define f13 45
117 # define f14 46
118 # define f15 47
119 # define f16 48
120 # define f17 49
121 # define f18 50
122 # define f19 51
123 # define f20 52
124 # define f21 53
125 # define f22 54
126 # define f23 55
127 # define f24 56
128 # define f25 57
129 # define f26 58
130 # define f27 59
131 # define f28 60
132 # define f29 61
133 # define f30 62
134 # define f31 63
135 # else
136 # define fr0 32
137 # define fr1 33
138 # define fr2 34
139 # define fr3 35
140 # define fr4 36
141 # define fr5 37
142 # define fr6 38
143 # define fr7 39
144 # define fr8 40
145 # define fr9 41
146 # define fr10 42
147 # define fr11 43
148 # define fr12 44
149 # define fr13 45
150 # define fr14 46
151 # define fr15 47
152 # define fr16 48
153 # define fr17 49
154 # define fr18 50
155 # define fr19 51
156 # define fr20 52
157 # define fr21 53
158 # define fr22 54
159 # define fr23 55
160 # define fr24 56
161 # define fr25 57
162 # define fr26 58
163 # define fr27 59
164 # define fr28 60
165 # define fr29 61
166 # define fr30 62
167 # define fr31 63
168 # endif
169
170 #elif MACHREGS_sparc
171
172 # define g0 0
173 # define g1 1
174 # define g2 2
175 # define g3 3
176 # define g4 4
177 # define g5 5
178 # define g6 6
179 # define g7 7
180
181 # define o0 8
182 # define o1 9
183 # define o2 10
184 # define o3 11
185 # define o4 12
186 # define o5 13
187 # define o6 14
188 # define o7 15
189
190 # define l0 16
191 # define l1 17
192 # define l2 18
193 # define l3 19
194 # define l4 20
195 # define l5 21
196 # define l6 22
197 # define l7 23
198
199 # define i0 24
200 # define i1 25
201 # define i2 26
202 # define i3 27
203 # define i4 28
204 # define i5 29
205 # define i6 30
206 # define i7 31
207
208 # define f0 32
209 # define f1 33
210 # define f2 34
211 # define f3 35
212 # define f4 36
213 # define f5 37
214 # define f6 38
215 # define f7 39
216 # define f8 40
217 # define f9 41
218 # define f10 42
219 # define f11 43
220 # define f12 44
221 # define f13 45
222 # define f14 46
223 # define f15 47
224 # define f16 48
225 # define f17 49
226 # define f18 50
227 # define f19 51
228 # define f20 52
229 # define f21 53
230 # define f22 54
231 # define f23 55
232 # define f24 56
233 # define f25 57
234 # define f26 58
235 # define f27 59
236 # define f28 60
237 # define f29 61
238 # define f30 62
239 # define f31 63
240
241 #endif
242
243 callerSaves :: GlobalReg -> Bool
244 #ifdef CALLER_SAVES_Base
245 callerSaves BaseReg = True
246 #endif
247 #ifdef CALLER_SAVES_R1
248 callerSaves (VanillaReg 1 _) = True
249 #endif
250 #ifdef CALLER_SAVES_R2
251 callerSaves (VanillaReg 2 _) = True
252 #endif
253 #ifdef CALLER_SAVES_R3
254 callerSaves (VanillaReg 3 _) = True
255 #endif
256 #ifdef CALLER_SAVES_R4
257 callerSaves (VanillaReg 4 _) = True
258 #endif
259 #ifdef CALLER_SAVES_R5
260 callerSaves (VanillaReg 5 _) = True
261 #endif
262 #ifdef CALLER_SAVES_R6
263 callerSaves (VanillaReg 6 _) = True
264 #endif
265 #ifdef CALLER_SAVES_R7
266 callerSaves (VanillaReg 7 _) = True
267 #endif
268 #ifdef CALLER_SAVES_R8
269 callerSaves (VanillaReg 8 _) = True
270 #endif
271 #ifdef CALLER_SAVES_R9
272 callerSaves (VanillaReg 9 _) = True
273 #endif
274 #ifdef CALLER_SAVES_R10
275 callerSaves (VanillaReg 10 _) = True
276 #endif
277 #ifdef CALLER_SAVES_F1
278 callerSaves (FloatReg 1) = True
279 #endif
280 #ifdef CALLER_SAVES_F2
281 callerSaves (FloatReg 2) = True
282 #endif
283 #ifdef CALLER_SAVES_F3
284 callerSaves (FloatReg 3) = True
285 #endif
286 #ifdef CALLER_SAVES_F4
287 callerSaves (FloatReg 4) = True
288 #endif
289 #ifdef CALLER_SAVES_F5
290 callerSaves (FloatReg 5) = True
291 #endif
292 #ifdef CALLER_SAVES_F6
293 callerSaves (FloatReg 6) = True
294 #endif
295 #ifdef CALLER_SAVES_D1
296 callerSaves (DoubleReg 1) = True
297 #endif
298 #ifdef CALLER_SAVES_D2
299 callerSaves (DoubleReg 2) = True
300 #endif
301 #ifdef CALLER_SAVES_D3
302 callerSaves (DoubleReg 3) = True
303 #endif
304 #ifdef CALLER_SAVES_D4
305 callerSaves (DoubleReg 4) = True
306 #endif
307 #ifdef CALLER_SAVES_D5
308 callerSaves (DoubleReg 5) = True
309 #endif
310 #ifdef CALLER_SAVES_D6
311 callerSaves (DoubleReg 6) = True
312 #endif
313 #ifdef CALLER_SAVES_L1
314 callerSaves (LongReg 1) = True
315 #endif
316 #ifdef CALLER_SAVES_Sp
317 callerSaves Sp = True
318 #endif
319 #ifdef CALLER_SAVES_SpLim
320 callerSaves SpLim = True
321 #endif
322 #ifdef CALLER_SAVES_Hp
323 callerSaves Hp = True
324 #endif
325 #ifdef CALLER_SAVES_HpLim
326 callerSaves HpLim = True
327 #endif
328 #ifdef CALLER_SAVES_CCCS
329 callerSaves CCCS = True
330 #endif
331 #ifdef CALLER_SAVES_CurrentTSO
332 callerSaves CurrentTSO = True
333 #endif
334 #ifdef CALLER_SAVES_CurrentNursery
335 callerSaves CurrentNursery = True
336 #endif
337 callerSaves _ = False
338
339 activeStgRegs :: [GlobalReg]
340 activeStgRegs = [
341 #ifdef REG_Base
342 BaseReg
343 #endif
344 #ifdef REG_Sp
345 ,Sp
346 #endif
347 #ifdef REG_Hp
348 ,Hp
349 #endif
350 #ifdef REG_R1
351 ,VanillaReg 1 VGcPtr
352 #endif
353 #ifdef REG_R2
354 ,VanillaReg 2 VGcPtr
355 #endif
356 #ifdef REG_R3
357 ,VanillaReg 3 VGcPtr
358 #endif
359 #ifdef REG_R4
360 ,VanillaReg 4 VGcPtr
361 #endif
362 #ifdef REG_R5
363 ,VanillaReg 5 VGcPtr
364 #endif
365 #ifdef REG_R6
366 ,VanillaReg 6 VGcPtr
367 #endif
368 #ifdef REG_R7
369 ,VanillaReg 7 VGcPtr
370 #endif
371 #ifdef REG_R8
372 ,VanillaReg 8 VGcPtr
373 #endif
374 #ifdef REG_R9
375 ,VanillaReg 9 VGcPtr
376 #endif
377 #ifdef REG_R10
378 ,VanillaReg 10 VGcPtr
379 #endif
380 #ifdef REG_SpLim
381 ,SpLim
382 #endif
383 #if MAX_REAL_SSE_REG != 0
384 #ifdef REG_F1
385 ,FloatReg 1
386 #endif
387 #ifdef REG_D1
388 ,DoubleReg 1
389 #endif
390 #ifdef REG_F2
391 ,FloatReg 2
392 #endif
393 #ifdef REG_D2
394 ,DoubleReg 2
395 #endif
396 #ifdef REG_F3
397 ,FloatReg 3
398 #endif
399 #ifdef REG_D3
400 ,DoubleReg 3
401 #endif
402 #ifdef REG_F4
403 ,FloatReg 4
404 #endif
405 #ifdef REG_D4
406 ,DoubleReg 4
407 #endif
408 #ifdef REG_F5
409 ,FloatReg 5
410 #endif
411 #ifdef REG_D5
412 ,DoubleReg 5
413 #endif
414 #ifdef REG_F6
415 ,FloatReg 6
416 #endif
417 #ifdef REG_D6
418 ,DoubleReg 6
419 #endif
420 #else /* MAX_REAL_SSE_REG == 0 */
421 #ifdef REG_F1
422 ,FloatReg 1
423 #endif
424 #ifdef REG_F2
425 ,FloatReg 2
426 #endif
427 #ifdef REG_F3
428 ,FloatReg 3
429 #endif
430 #ifdef REG_F4
431 ,FloatReg 4
432 #endif
433 #ifdef REG_F5
434 ,FloatReg 5
435 #endif
436 #ifdef REG_F6
437 ,FloatReg 6
438 #endif
439 #ifdef REG_D1
440 ,DoubleReg 1
441 #endif
442 #ifdef REG_D2
443 ,DoubleReg 2
444 #endif
445 #ifdef REG_D3
446 ,DoubleReg 3
447 #endif
448 #ifdef REG_D4
449 ,DoubleReg 4
450 #endif
451 #ifdef REG_D5
452 ,DoubleReg 5
453 #endif
454 #ifdef REG_D6
455 ,DoubleReg 6
456 #endif
457 #endif /* MAX_REAL_SSE_REG == 0 */
458 ]
459
460 haveRegBase :: Bool
461 #ifdef REG_Base
462 haveRegBase = True
463 #else
464 haveRegBase = False
465 #endif
466
467 -- | Returns 'Nothing' if this global register is not stored
468 -- in a real machine register, otherwise returns @'Just' reg@, where
469 -- reg is the machine register it is stored in.
470 globalRegMaybe :: GlobalReg -> Maybe RealReg
471 #if MACHREGS_i386 || MACHREGS_x86_64 || MACHREGS_sparc || MACHREGS_powerpc
472 # ifdef REG_Base
473 globalRegMaybe BaseReg = Just (RealRegSingle REG_Base)
474 # endif
475 # ifdef REG_R1
476 globalRegMaybe (VanillaReg 1 _) = Just (RealRegSingle REG_R1)
477 # endif
478 # ifdef REG_R2
479 globalRegMaybe (VanillaReg 2 _) = Just (RealRegSingle REG_R2)
480 # endif
481 # ifdef REG_R3
482 globalRegMaybe (VanillaReg 3 _) = Just (RealRegSingle REG_R3)
483 # endif
484 # ifdef REG_R4
485 globalRegMaybe (VanillaReg 4 _) = Just (RealRegSingle REG_R4)
486 # endif
487 # ifdef REG_R5
488 globalRegMaybe (VanillaReg 5 _) = Just (RealRegSingle REG_R5)
489 # endif
490 # ifdef REG_R6
491 globalRegMaybe (VanillaReg 6 _) = Just (RealRegSingle REG_R6)
492 # endif
493 # ifdef REG_R7
494 globalRegMaybe (VanillaReg 7 _) = Just (RealRegSingle REG_R7)
495 # endif
496 # ifdef REG_R8
497 globalRegMaybe (VanillaReg 8 _) = Just (RealRegSingle REG_R8)
498 # endif
499 # ifdef REG_R9
500 globalRegMaybe (VanillaReg 9 _) = Just (RealRegSingle REG_R9)
501 # endif
502 # ifdef REG_R10
503 globalRegMaybe (VanillaReg 10 _) = Just (RealRegSingle REG_R10)
504 # endif
505 # ifdef REG_F1
506 globalRegMaybe (FloatReg 1) = Just (RealRegSingle REG_F1)
507 # endif
508 # ifdef REG_F2
509 globalRegMaybe (FloatReg 2) = Just (RealRegSingle REG_F2)
510 # endif
511 # ifdef REG_F3
512 globalRegMaybe (FloatReg 3) = Just (RealRegSingle REG_F3)
513 # endif
514 # ifdef REG_F4
515 globalRegMaybe (FloatReg 4) = Just (RealRegSingle REG_F4)
516 # endif
517 # ifdef REG_F5
518 globalRegMaybe (FloatReg 5) = Just (RealRegSingle REG_F5)
519 # endif
520 # ifdef REG_F6
521 globalRegMaybe (FloatReg 6) = Just (RealRegSingle REG_F6)
522 # endif
523 # ifdef REG_D1
524 globalRegMaybe (DoubleReg 1) =
525 # if MACHREGS_sparc
526 Just (RealRegPair REG_D1 (REG_D1 + 1))
527 # else
528 Just (RealRegSingle REG_D1)
529 # endif
530 # endif
531 # ifdef REG_D2
532 globalRegMaybe (DoubleReg 2) =
533 # if MACHREGS_sparc
534 Just (RealRegPair REG_D2 (REG_D2 + 1))
535 # else
536 Just (RealRegSingle REG_D2)
537 # endif
538 # endif
539 # ifdef REG_D3
540 globalRegMaybe (DoubleReg 3) =
541 # if MACHREGS_sparc
542 Just (RealRegPair REG_D3 (REG_D3 + 1))
543 # else
544 Just (RealRegSingle REG_D3)
545 # endif
546 # endif
547 # ifdef REG_D4
548 globalRegMaybe (DoubleReg 4) =
549 # if MACHREGS_sparc
550 Just (RealRegPair REG_D4 (REG_D4 + 1))
551 # else
552 Just (RealRegSingle REG_D4)
553 # endif
554 # endif
555 # ifdef REG_D5
556 globalRegMaybe (DoubleReg 5) =
557 # if MACHREGS_sparc
558 Just (RealRegPair REG_D5 (REG_D5 + 1))
559 # else
560 Just (RealRegSingle REG_D5)
561 # endif
562 # endif
563 # ifdef REG_D6
564 globalRegMaybe (DoubleReg 6) =
565 # if MACHREGS_sparc
566 Just (RealRegPair REG_D6 (REG_D6 + 1))
567 # else
568 Just (RealRegSingle REG_D6)
569 # endif
570 # endif
571 # ifdef REG_Sp
572 globalRegMaybe Sp = Just (RealRegSingle REG_Sp)
573 # endif
574 # ifdef REG_Lng1
575 globalRegMaybe (LongReg 1) = Just (RealRegSingle REG_Lng1)
576 # endif
577 # ifdef REG_Lng2
578 globalRegMaybe (LongReg 2) = Just (RealRegSingle REG_Lng2)
579 # endif
580 # ifdef REG_SpLim
581 globalRegMaybe SpLim = Just (RealRegSingle REG_SpLim)
582 # endif
583 # ifdef REG_Hp
584 globalRegMaybe Hp = Just (RealRegSingle REG_Hp)
585 # endif
586 # ifdef REG_HpLim
587 globalRegMaybe HpLim = Just (RealRegSingle REG_HpLim)
588 # endif
589 # ifdef REG_CurrentTSO
590 globalRegMaybe CurrentTSO = Just (RealRegSingle REG_CurrentTSO)
591 # endif
592 # ifdef REG_CurrentNursery
593 globalRegMaybe CurrentNursery = Just (RealRegSingle REG_CurrentNursery)
594 # endif
595 globalRegMaybe _ = Nothing
596 #else
597 globalRegMaybe = panic "globalRegMaybe not defined for this platform"
598 #endif
599
600 freeReg :: RegNo -> FastBool
601
602 #if MACHREGS_i386 || MACHREGS_x86_64
603
604 # if MACHREGS_i386
605 freeReg esp = fastBool False -- %esp is the C stack pointer
606 freeReg esi = fastBool False -- Note [esi/edi not allocatable]
607 freeReg edi = fastBool False
608 # endif
609 # if MACHREGS_x86_64
610 freeReg rsp = fastBool False -- %rsp is the C stack pointer
611 # endif
612
613 {-
614 Note [esi/edi not allocatable]
615
616 %esi is mapped to R1, so %esi would normally be allocatable while it
617 is not being used for R1. However, %esi has no 8-bit version on x86,
618 and the linear register allocator is not sophisticated enough to
619 handle this irregularity (we need more RegClasses). The
620 graph-colouring allocator also cannot handle this - it was designed
621 with more flexibility in mind, but the current implementation is
622 restricted to the same set of classes as the linear allocator.
623
624 Hence, on x86 esi and edi are treated as not allocatable.
625 -}
626
627 -- split patterns in two functions to prevent overlaps
628 freeReg r = freeRegBase r
629
630 freeRegBase :: RegNo -> FastBool
631 # ifdef REG_Base
632 freeRegBase REG_Base = fastBool False
633 # endif
634 # ifdef REG_Sp
635 freeRegBase REG_Sp = fastBool False
636 # endif
637 # ifdef REG_SpLim
638 freeRegBase REG_SpLim = fastBool False
639 # endif
640 # ifdef REG_Hp
641 freeRegBase REG_Hp = fastBool False
642 # endif
643 # ifdef REG_HpLim
644 freeRegBase REG_HpLim = fastBool False
645 # endif
646 -- All other regs are considered to be "free", because we can track
647 -- their liveness accurately.
648 freeRegBase _ = fastBool True
649
650 #elif MACHREGS_powerpc
651
652 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns,
653 -- but it's actually free
654 freeReg 1 = fastBool False -- The Stack Pointer
655 # if !MACHREGS_darwin
656 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
657 freeReg 2 = fastBool False
658 # endif
659 # ifdef REG_Base
660 freeReg REG_Base = fastBool False
661 # endif
662 # ifdef REG_R1
663 freeReg REG_R1 = fastBool False
664 # endif
665 # ifdef REG_R2
666 freeReg REG_R2 = fastBool False
667 # endif
668 # ifdef REG_R3
669 freeReg REG_R3 = fastBool False
670 # endif
671 # ifdef REG_R4
672 freeReg REG_R4 = fastBool False
673 # endif
674 # ifdef REG_R5
675 freeReg REG_R5 = fastBool False
676 # endif
677 # ifdef REG_R6
678 freeReg REG_R6 = fastBool False
679 # endif
680 # ifdef REG_R7
681 freeReg REG_R7 = fastBool False
682 # endif
683 # ifdef REG_R8
684 freeReg REG_R8 = fastBool False
685 # endif
686 # ifdef REG_R9
687 freeReg REG_R9 = fastBool False
688 # endif
689 # ifdef REG_R10
690 freeReg REG_R10 = fastBool False
691 # endif
692 # ifdef REG_F1
693 freeReg REG_F1 = fastBool False
694 # endif
695 # ifdef REG_F2
696 freeReg REG_F2 = fastBool False
697 # endif
698 # ifdef REG_F3
699 freeReg REG_F3 = fastBool False
700 # endif
701 # ifdef REG_F4
702 freeReg REG_F4 = fastBool False
703 # endif
704 # ifdef REG_F5
705 freeReg REG_F5 = fastBool False
706 # endif
707 # ifdef REG_F6
708 freeReg REG_F6 = fastBool False
709 # endif
710 # ifdef REG_D1
711 freeReg REG_D1 = fastBool False
712 # endif
713 # ifdef REG_D2
714 freeReg REG_D2 = fastBool False
715 # endif
716 # ifdef REG_D3
717 freeReg REG_D3 = fastBool False
718 # endif
719 # ifdef REG_D4
720 freeReg REG_D4 = fastBool False
721 # endif
722 # ifdef REG_D5
723 freeReg REG_D5 = fastBool False
724 # endif
725 # ifdef REG_D6
726 freeReg REG_D6 = fastBool False
727 # endif
728 # ifdef REG_Sp
729 freeReg REG_Sp = fastBool False
730 # endif
731 # ifdef REG_Su
732 freeReg REG_Su = fastBool False
733 # endif
734 # ifdef REG_SpLim
735 freeReg REG_SpLim = fastBool False
736 # endif
737 # ifdef REG_Hp
738 freeReg REG_Hp = fastBool False
739 # endif
740 # ifdef REG_HpLim
741 freeReg REG_HpLim = fastBool False
742 # endif
743 freeReg _ = fastBool True
744
745 #elif MACHREGS_sparc
746
747 -- SPARC regs used by the OS / ABI
748 -- %g0(r0) is always zero
749 freeReg g0 = fastBool False
750
751 -- %g5(r5) - %g7(r7)
752 -- are reserved for the OS
753 freeReg g5 = fastBool False
754 freeReg g6 = fastBool False
755 freeReg g7 = fastBool False
756
757 -- %o6(r14)
758 -- is the C stack pointer
759 freeReg o6 = fastBool False
760
761 -- %o7(r15)
762 -- holds the C return address
763 freeReg o7 = fastBool False
764
765 -- %i6(r30)
766 -- is the C frame pointer
767 freeReg i6 = fastBool False
768
769 -- %i7(r31)
770 -- is used for C return addresses
771 freeReg i7 = fastBool False
772
773 -- %f0(r32) - %f1(r32)
774 -- are C floating point return regs
775 freeReg f0 = fastBool False
776 freeReg f1 = fastBool False
777
778 {-
779 freeReg regNo
780 -- don't release high half of double regs
781 | regNo >= f0
782 , regNo < NCG_FirstFloatReg
783 , regNo `mod` 2 /= 0
784 = fastBool False
785 -}
786
787 # ifdef REG_Base
788 freeReg REG_Base = fastBool False
789 # endif
790 # ifdef REG_R1
791 freeReg REG_R1 = fastBool False
792 # endif
793 # ifdef REG_R2
794 freeReg REG_R2 = fastBool False
795 # endif
796 # ifdef REG_R3
797 freeReg REG_R3 = fastBool False
798 # endif
799 # ifdef REG_R4
800 freeReg REG_R4 = fastBool False
801 # endif
802 # ifdef REG_R5
803 freeReg REG_R5 = fastBool False
804 # endif
805 # ifdef REG_R6
806 freeReg REG_R6 = fastBool False
807 # endif
808 # ifdef REG_R7
809 freeReg REG_R7 = fastBool False
810 # endif
811 # ifdef REG_R8
812 freeReg REG_R8 = fastBool False
813 # endif
814 # ifdef REG_R9
815 freeReg REG_R9 = fastBool False
816 # endif
817 # ifdef REG_R10
818 freeReg REG_R10 = fastBool False
819 # endif
820 # ifdef REG_F1
821 freeReg REG_F1 = fastBool False
822 # endif
823 # ifdef REG_F2
824 freeReg REG_F2 = fastBool False
825 # endif
826 # ifdef REG_F3
827 freeReg REG_F3 = fastBool False
828 # endif
829 # ifdef REG_F4
830 freeReg REG_F4 = fastBool False
831 # endif
832 # ifdef REG_F5
833 freeReg REG_F5 = fastBool False
834 # endif
835 # ifdef REG_F6
836 freeReg REG_F6 = fastBool False
837 # endif
838 # ifdef REG_D1
839 freeReg REG_D1 = fastBool False
840 # endif
841 # ifdef REG_D1_2
842 freeReg REG_D1_2 = fastBool False
843 # endif
844 # ifdef REG_D2
845 freeReg REG_D2 = fastBool False
846 # endif
847 # ifdef REG_D2_2
848 freeReg REG_D2_2 = fastBool False
849 # endif
850 # ifdef REG_D3
851 freeReg REG_D3 = fastBool False
852 # endif
853 # ifdef REG_D3_2
854 freeReg REG_D3_2 = fastBool False
855 # endif
856 # ifdef REG_D4
857 freeReg REG_D4 = fastBool False
858 # endif
859 # ifdef REG_D4_2
860 freeReg REG_D4_2 = fastBool False
861 # endif
862 # ifdef REG_D5
863 freeReg REG_D5 = fastBool False
864 # endif
865 # ifdef REG_D5_2
866 freeReg REG_D5_2 = fastBool False
867 # endif
868 # ifdef REG_D6
869 freeReg REG_D6 = fastBool False
870 # endif
871 # ifdef REG_D6_2
872 freeReg REG_D6_2 = fastBool False
873 # endif
874 # ifdef REG_Sp
875 freeReg REG_Sp = fastBool False
876 # endif
877 # ifdef REG_Su
878 freeReg REG_Su = fastBool False
879 # endif
880 # ifdef REG_SpLim
881 freeReg REG_SpLim = fastBool False
882 # endif
883 # ifdef REG_Hp
884 freeReg REG_Hp = fastBool False
885 # endif
886 # ifdef REG_HpLim
887 freeReg REG_HpLim = fastBool False
888 # endif
889 freeReg _ = fastBool True
890
891 #else
892
893 freeReg = panic "freeReg not defined for this platform"
894
895 #endif
896