Fix warnings with newer gcc versions (I hope)
[ghc.git] / includes / SMP.h
1 /* ----------------------------------------------------------------------------
2 *
3 * (c) The GHC Team, 2005
4 *
5 * Macros for THREADED_RTS support
6 *
7 * -------------------------------------------------------------------------- */
8
9 #ifndef SMP_H
10 #define SMP_H
11
12 /* THREADED_RTS is currently not compatible with the following options:
13 *
14 * PROFILING (but only 1 CPU supported)
15 * TICKY_TICKY
16 * Unregisterised builds are ok, but only 1 CPU supported.
17 */
18
19 #ifdef CMINUSMINUS
20
21 #define unlockClosure(ptr,info) \
22 prim %write_barrier() []; \
23 StgHeader_info(ptr) = info;
24
25 #else
26
27 #if defined(THREADED_RTS)
28
29 #if defined(TICKY_TICKY)
30 #error Build options incompatible with THREADED_RTS.
31 #endif
32
33 /* ----------------------------------------------------------------------------
34 Atomic operations
35 ------------------------------------------------------------------------- */
36
37 /*
38 * The atomic exchange operation: xchg(p,w) exchanges the value
39 * pointed to by p with the value w, returning the old value.
40 *
41 * Used for locking closures during updates (see lockClosure() below)
42 * and the MVar primops.
43 */
44 INLINE_HEADER StgWord xchg(StgPtr p, StgWord w);
45
46 /*
47 * Compare-and-swap. Atomically does this:
48 *
49 * cas(p,o,n) {
50 * r = *p;
51 * if (r == o) { *p = n };
52 * return r;
53 * }
54 */
55 INLINE_HEADER StgWord cas(StgVolatilePtr p, StgWord o, StgWord n);
56
57 /*
58 * Prevents write operations from moving across this call in either
59 * direction.
60 */
61 INLINE_HEADER void write_barrier(void);
62
63 /* ----------------------------------------------------------------------------
64 Implementations
65 ------------------------------------------------------------------------- */
66 /*
67 * NB: the xchg instruction is implicitly locked, so we do not need
68 * a lock prefix here.
69 */
70 INLINE_HEADER StgWord
71 xchg(StgPtr p, StgWord w)
72 {
73 StgWord result;
74 #if i386_HOST_ARCH || x86_64_HOST_ARCH
75 result = w;
76 __asm__ __volatile__ (
77 "xchg %1,%0"
78 :"+r" (result), "+m" (*p)
79 : /* no input-only operands */
80 );
81 #elif powerpc_HOST_ARCH
82 __asm__ __volatile__ (
83 "1: lwarx %0, 0, %2\n"
84 " stwcx. %1, 0, %2\n"
85 " bne- 1b"
86 :"=&r" (result)
87 :"r" (w), "r" (p)
88 );
89 #elif sparc_HOST_ARCH
90 result = w;
91 __asm__ __volatile__ (
92 "swap %1,%0"
93 : "+r" (result), "+m" (*p)
94 : /* no input-only operands */
95 );
96 #elif !defined(WITHSMP)
97 result = *p;
98 *p = w;
99 #else
100 #error xchg() unimplemented on this architecture
101 #endif
102 return result;
103 }
104
105 /*
106 * CMPXCHG - the single-word atomic compare-and-exchange instruction. Used
107 * in the STM implementation.
108 */
109 INLINE_HEADER StgWord
110 cas(StgVolatilePtr p, StgWord o, StgWord n)
111 {
112 #if i386_HOST_ARCH || x86_64_HOST_ARCH
113 __asm__ __volatile__ (
114 "lock\ncmpxchg %3,%1"
115 :"=a"(o), "=m" (*(volatile unsigned int *)p)
116 :"0" (o), "r" (n));
117 return o;
118 #elif powerpc_HOST_ARCH
119 StgWord result;
120 __asm__ __volatile__ (
121 "1: lwarx %0, 0, %3\n"
122 " cmpw %0, %1\n"
123 " bne 2f\n"
124 " stwcx. %2, 0, %3\n"
125 " bne- 1b\n"
126 "2:"
127 :"=&r" (result)
128 :"r" (o), "r" (n), "r" (p)
129 :"cc", "memory"
130 );
131 return result;
132 #elif sparc_HOST_ARCH
133 __asm__ __volatile__ (
134 "cas [%1], %2, %0"
135 : "+r" (n)
136 : "r" (p), "r" (o)
137 : "memory"
138 );
139 return n;
140 #elif !defined(WITHSMP)
141 StgWord result;
142 result = *p;
143 if (result == o) {
144 *p = n;
145 }
146 return result;
147 #else
148 #error cas() unimplemented on this architecture
149 #endif
150 }
151
152 /*
153 * Write barrier - ensure that all preceding writes have happened
154 * before all following writes.
155 *
156 * We need to tell both the compiler AND the CPU about the barrier.
157 * This is a brute force solution; better results might be obtained by
158 * using volatile type declarations to get fine-grained ordering
159 * control in C, and optionally a memory barrier instruction on CPUs
160 * that require it (not x86 or x86_64).
161 */
162 INLINE_HEADER void
163 write_barrier(void) {
164 #if i386_HOST_ARCH || x86_64_HOST_ARCH
165 __asm__ __volatile__ ("" : : : "memory");
166 #elif powerpc_HOST_ARCH
167 __asm__ __volatile__ ("lwsync" : : : "memory");
168 #elif sparc_HOST_ARCH
169 /* Sparc in TSO mode does not require write/write barriers. */
170 __asm__ __volatile__ ("" : : : "memory");
171 #elif !defined(WITHSMP)
172 return;
173 #else
174 #error memory barriers unimplemented on this architecture
175 #endif
176 }
177
178 /* -----------------------------------------------------------------------------
179 * Locking/unlocking closures
180 *
181 * This is used primarily in the implementation of MVars.
182 * -------------------------------------------------------------------------- */
183
184 #define SPIN_COUNT 4000
185
186 #ifdef KEEP_LOCKCLOSURE
187 // We want a callable copy of lockClosure() so that we can refer to it
188 // from .cmm files compiled using the native codegen.
189 extern StgInfoTable *lockClosure(StgClosure *p);
190 INLINE_ME
191 #else
192 INLINE_HEADER
193 #endif
194 StgInfoTable *
195 lockClosure(StgClosure *p)
196 {
197 StgWord info;
198 do {
199 nat i = 0;
200 do {
201 info = xchg((P_)(void *)&p->header.info, (W_)&stg_WHITEHOLE_info);
202 if (info != (W_)&stg_WHITEHOLE_info) return (StgInfoTable *)info;
203 } while (++i < SPIN_COUNT);
204 yieldThread();
205 } while (1);
206 }
207
208 INLINE_HEADER void
209 unlockClosure(StgClosure *p, const StgInfoTable *info)
210 {
211 // This is a strictly ordered write, so we need a write_barrier():
212 write_barrier();
213 p->header.info = info;
214 }
215
216 /* -----------------------------------------------------------------------------
217 * Spin locks
218 *
219 * These are simple spin-only locks as opposed to Mutexes which
220 * probably spin for a while before blocking in the kernel. We use
221 * these when we are sure that all our threads are actively running on
222 * a CPU, eg. in the GC.
223 *
224 * TODO: measure whether we really need these, or whether Mutexes
225 * would do (and be a bit safer if a CPU becomes loaded).
226 * -------------------------------------------------------------------------- */
227
228 #if defined(DEBUG)
229 typedef struct StgSync_
230 {
231 StgWord32 lock;
232 StgWord64 spin; // DEBUG version counts how much it spins
233 } StgSync;
234 #else
235 typedef StgWord StgSync;
236 #endif
237
238 typedef lnat StgSyncCount;
239
240
241 #if defined(DEBUG)
242
243 // Debug versions of spin locks maintain a spin count
244
245 // How to use:
246 // To use the debug veriosn of the spin locks, a debug version of the program
247 // can be run under a deugger with a break point on stat_exit. At exit time
248 // of the program one can examine the state the spin count counts of various
249 // spin locks to check for contention.
250
251 // acquire spin lock
252 INLINE_HEADER void ACQUIRE_SPIN_LOCK(StgSync * p)
253 {
254 StgWord32 r = 0;
255 do {
256 p->spin++;
257 r = cas((StgVolatilePtr)&(p->lock), 1, 0);
258 } while(r == 0);
259 p->spin--;
260 }
261
262 // release spin lock
263 INLINE_HEADER void RELEASE_SPIN_LOCK(StgSync * p)
264 {
265 write_barrier();
266 p->lock = 1;
267 }
268
269 // initialise spin lock
270 INLINE_HEADER void initSpinLock(StgSync * p)
271 {
272 write_barrier();
273 p->lock = 1;
274 p->spin = 0;
275 }
276
277 #else
278
279 // acquire spin lock
280 INLINE_HEADER void ACQUIRE_SPIN_LOCK(StgSync * p)
281 {
282 StgWord32 r = 0;
283 do {
284 r = cas((StgVolatilePtr)p, 1, 0);
285 } while(r == 0);
286 }
287
288 // release spin lock
289 INLINE_HEADER void RELEASE_SPIN_LOCK(StgSync * p)
290 {
291 write_barrier();
292 (*p) = 1;
293 }
294
295 // init spin lock
296 INLINE_HEADER void initSpinLock(StgSync * p)
297 {
298 write_barrier();
299 (*p) = 1;
300 }
301
302 #endif /* DEBUG */
303
304 /* ---------------------------------------------------------------------- */
305 #else /* !THREADED_RTS */
306
307 #define write_barrier() /* nothing */
308
309 INLINE_HEADER StgWord
310 xchg(StgPtr p, StgWord w)
311 {
312 StgWord old = *p;
313 *p = w;
314 return old;
315 }
316
317 INLINE_HEADER StgInfoTable *
318 lockClosure(StgClosure *p)
319 { return (StgInfoTable *)p->header.info; }
320
321 INLINE_HEADER void
322 unlockClosure(StgClosure *p STG_UNUSED, const StgInfoTable *info STG_UNUSED)
323 { /* nothing */ }
324
325 // Using macros here means we don't have to ensure the argument is in scope
326 #define ACQUIRE_SPIN_LOCK(p) /* nothing */
327 #define RELEASE_SPIN_LOCK(p) /* nothing */
328
329 INLINE_HEADER void initSpinLock(void * p STG_UNUSED)
330 { /* nothing */ }
331
332 #endif /* !THREADED_RTS */
333
334 // Handy specialised versions of lockClosure()/unlockClosure()
335 INLINE_HEADER void lockTSO(StgTSO *tso)
336 { lockClosure((StgClosure *)tso); }
337
338 INLINE_HEADER void unlockTSO(StgTSO *tso)
339 { unlockClosure((StgClosure*)tso, (const StgInfoTable *)&stg_TSO_info); }
340
341 #endif /* SMP_H */
342
343 #endif /* CMINUSMINUS */