move the "meat" into the wiki, this file just contains pointers now
[ghc.git] / includes / MachRegs.h
1 /* -----------------------------------------------------------------------------
2 *
3 * (c) The GHC Team, 1998-1999
4 *
5 * Registers used in STG code. Might or might not correspond to
6 * actual machine registers.
7 *
8 * ---------------------------------------------------------------------------*/
9
10 #ifndef MACHREGS_H
11 #define MACHREGS_H
12
13 /* This file is #included into Haskell code in the compiler: #defines
14 * only in here please.
15 */
16
17 /*
18 * Defining NO_REGS causes no global registers to be used. NO_REGS is
19 * typically defined by GHC, via a command-line option passed to gcc,
20 * when the -funregisterised flag is given.
21 *
22 * NB. When NO_REGS is on, calling & return conventions may be
23 * different. For example, all function arguments will be passed on
24 * the stack, and components of an unboxed tuple will be returned on
25 * the stack rather than in registers.
26 */
27 #ifndef NO_REGS
28
29 /* NOTE: when testing the platform in this file we must test either
30 * *_HOST_ARCH and *_TARGET_ARCH, depending on whether COMPILING_GHC
31 * is set. This is because when we're compiling the RTS and HC code,
32 * the platform we're running on is the HOST, but when compiling GHC
33 * we want to know about the register mapping on the TARGET platform.
34 */
35 #ifdef COMPILING_GHC
36 #define alpha_REGS alpha_TARGET_ARCH
37 #define hppa1_1_REGS hppa1_1_TARGET_ARCH
38 #define i386_REGS i386_TARGET_ARCH
39 #define x86_64_REGS x86_64_TARGET_ARCH
40 #define m68k_REGS m68k_TARGET_ARCH
41 #define mips_REGS (mipsel_TARGET_ARCH || mipseb_TARGET_ARCH)
42 #define powerpc_REGS (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH)
43 #define ia64_REGS ia64_TARGET_ARCH
44 #define sparc_REGS sparc_TARGET_ARCH
45 #define darwin_REGS darwin_TARGET_OS
46 #else
47 #define alpha_REGS alpha_HOST_ARCH
48 #define hppa1_1_REGS hppa1_1_HOST_ARCH
49 #define i386_REGS i386_HOST_ARCH
50 #define x86_64_REGS x86_64_HOST_ARCH
51 #define m68k_REGS m68k_HOST_ARCH
52 #define mips_REGS (mipsel_HOST_ARCH || mipseb_HOST_ARCH)
53 #define powerpc_REGS (powerpc_HOST_ARCH || powerpc64_HOST_ARCH || rs6000_HOST_ARCH)
54 #define ia64_REGS ia64_HOST_ARCH
55 #define sparc_REGS sparc_HOST_ARCH
56 #define darwin_REGS darwin_HOST_OS
57 #endif
58
59 /* ----------------------------------------------------------------------------
60 Caller saves and callee-saves regs.
61
62 Caller-saves regs have to be saved around C-calls made from STG
63 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
64 is designated caller-saves in that machine's C calling convention.
65 -------------------------------------------------------------------------- */
66
67 /* -----------------------------------------------------------------------------
68 The DEC Alpha register mapping
69
70 Alpha registers
71 \tr{$9}--\tr{$14} are our ``prize'' callee-save registers.
72 \tr{$15} is the frame pointer, and \tr{$16}--\tr{$21} are argument
73 registers. (These are off-limits.) We can steal some of the \tr{$22}-and-up
74 caller-save registers provided we do the appropriate save/restore stuff.
75
76 \tr{$f2}--\tr{$f9} are some callee-save floating-point registers.
77
78 We cannot use \tr{$23} (aka t9), \tr{$24} (aka t10), \tr{$25} (aka
79 t11), \tr{$27} (aka pv), or \tr{$28} (aka at), because they are
80 occasionally required by the assembler to handle non-primitive
81 instructions (e.g. ldb, remq). Sigh!
82
83 Cheat sheet for GDB:
84
85 GDB here Main map
86 === ==== ========
87 s5 $14 R1
88 t1 $2 R2
89 t2 $3 R3
90 t3 $4 R4
91 t4 $5 R5
92 t5 $6 R6
93 t6 $7 R7
94 t7 $8 R8
95 s0 $9 Sp
96 s2 $11 SpLim
97 s3 $12 Hp
98 s4 $13 HpLim
99 t8 $22 NCG_reserved
100 t12 $27 NCG_reserved
101 -------------------------------------------------------------------------- */
102
103 #if alpha_REGS
104 # define REG(x) __asm__("$" #x)
105
106 # define CALLER_SAVES_R2
107 # define CALLER_SAVES_R3
108 # define CALLER_SAVES_R4
109 # define CALLER_SAVES_R5
110 # define CALLER_SAVES_R6
111 # define CALLER_SAVES_R7
112 # define CALLER_SAVES_R8
113
114 # define CALLER_SAVES_USER
115
116 # define REG_R1 14
117 # define REG_R2 2
118 # define REG_R3 3
119 # define REG_R4 4
120 # define REG_R5 5
121 # define REG_R6 6
122 # define REG_R7 7
123 # define REG_R8 8
124
125 # define REG_F1 f2
126 # define REG_F2 f3
127 # define REG_F3 f4
128 # define REG_F4 f5
129
130 # define REG_D1 f6
131 # define REG_D2 f7
132
133 # define REG_Sp 9
134 # define REG_SpLim 11
135
136 # define REG_Hp 12
137 # define REG_HpLim 13
138
139 # define NCG_Reserved_I1 22
140 # define NCG_Reserved_I2 27
141 # define NCG_Reserved_F1 f29
142 # define NCG_Reserved_F2 f30
143
144 #endif /* alpha_REGS */
145
146 /* -----------------------------------------------------------------------------
147 The HP-PA register mapping
148
149 We cater for HP-PA 1.1.
150
151 \tr{%r0}--\tr{%r1} are special.
152 \tr{%r2} is the return pointer.
153 \tr{%r3} is the frame pointer.
154 \tr{%r4}--\tr{%r18} are callee-save registers.
155 \tr{%r19} is a linkage table register for HPUX 8.0 shared libraries.
156 \tr{%r20}--\tr{%r22} are caller-save registers.
157 \tr{%r23}--\tr{%r26} are parameter registers.
158 \tr{%r27} is a global data pointer.
159 \tr{%r28}--\tr{%r29} are temporaries.
160 \tr{%r30} is the stack pointer.
161 \tr{%r31} is a temporary.
162
163 \tr{%fr12}--\tr{%fr15} are some callee-save floating-point registers.
164 \tr{%fr8}--\tr{%fr11} are some available caller-save fl-pt registers.
165 -------------------------------------------------------------------------- */
166
167 #if hppa1_1_REGS
168
169 #define REG(x) __asm__("%" #x)
170
171 #define REG_R1 r11
172 #define REG_R2 r12
173 #define REG_R3 r13
174 #define REG_R4 r14
175 #define REG_R5 r15
176 #define REG_R6 r16
177 #define REG_R7 r17
178 #define REG_R8 r18
179
180 #define REG_F1 fr12
181 #define REG_F2 fr12R
182 #define REG_F3 fr13
183 #define REG_F4 fr13R
184
185 #define REG_D1 fr20 /* L & R */
186 #define REG_D2 fr21 /* L & R */
187
188 #define REG_Sp r4
189 #define REG_SpLim r6
190
191 #define REG_Hp r7
192 #define REG_HpLim r8
193
194 #define NCG_Reserved_I1 r28
195 #define NCG_Reserved_I2 r29
196 #define NCG_Reserved_F1 fr8
197 #define NCG_Reserved_F2 fr8R
198 #define NCG_Reserved_D1 fr10
199 #define NCG_Reserved_D2 fr11
200
201 #endif /* hppa */
202
203 /* -----------------------------------------------------------------------------
204 The x86 register mapping
205
206 Ok, we've only got 6 general purpose registers, a frame pointer and a
207 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
208 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
209 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
210
211 Reg STG-Reg
212 ---------------
213 ebx Base
214 ebp Sp
215 esi R1
216 edi Hp
217
218 Leaving SpLim, and HpLim out of the picture.
219 -------------------------------------------------------------------------- */
220
221
222 #if i386_REGS
223
224 #define REG(x) __asm__("%" #x)
225
226 #ifndef not_doing_dynamic_linking
227 #define REG_Base ebx
228 #endif
229 #define REG_Sp ebp
230
231 #ifndef STOLEN_X86_REGS
232 #define STOLEN_X86_REGS 4
233 #endif
234
235 #if STOLEN_X86_REGS >= 3
236 # define REG_R1 esi
237 #endif
238
239 #if STOLEN_X86_REGS >= 4
240 # define REG_Hp edi
241 #endif
242
243 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
244 #define MAX_REAL_FLOAT_REG 0
245 #define MAX_REAL_DOUBLE_REG 0
246 #define MAX_REAL_LONG_REG 0
247
248 #endif /* iX86 */
249
250 /* -----------------------------------------------------------------------------
251 The x86-64 register mapping
252
253 %rax caller-saves, don't steal this one
254 %rbx YES
255 %rcx arg reg, caller-saves
256 %rdx arg reg, caller-saves
257 %rsi arg reg, caller-saves
258 %rdi arg reg, caller-saves
259 %rbp YES (our *prime* register)
260 %rsp (unavailable - stack pointer)
261 %r8 arg reg, caller-saves
262 %r9 arg reg, caller-saves
263 %r10 caller-saves
264 %r11 caller-saves
265 %r12 YES
266 %r13 YES
267 %r14 YES
268 %r15 YES
269
270 %xmm0-7 arg regs, caller-saves
271 %xmm8-15 caller-saves
272
273 Use the caller-saves regs for Rn, because we don't always have to
274 save those (as opposed to Sp/Hp/SpLim etc. which always have to be
275 saved).
276
277 --------------------------------------------------------------------------- */
278
279 #if x86_64_REGS
280
281 #define REG(x) __asm__("%" #x)
282
283 #define REG_Base r13
284 #define REG_Sp rbp
285 #define REG_Hp r12
286 #define REG_R1 rbx
287 #define REG_R2 rsi
288 #define REG_R3 rdi
289 #define REG_R4 r8
290 #define REG_R5 r9
291 #define REG_SpLim r14
292 #define REG_HpLim r15
293
294 #define REG_F1 xmm1
295 #define REG_F2 xmm2
296 #define REG_F3 xmm3
297 #define REG_F4 xmm4
298
299 #define REG_D1 xmm5
300 #define REG_D2 xmm6
301
302 #define CALLER_SAVES_R2
303 #define CALLER_SAVES_R3
304 #define CALLER_SAVES_R4
305 #define CALLER_SAVES_R5
306
307 #define CALLER_SAVES_F1
308 #define CALLER_SAVES_F2
309 #define CALLER_SAVES_F3
310 #define CALLER_SAVES_F4
311
312 #define CALLER_SAVES_D1
313 #define CALLER_SAVES_D2
314
315 #define MAX_REAL_VANILLA_REG 5
316 #define MAX_REAL_FLOAT_REG 4
317 #define MAX_REAL_DOUBLE_REG 2
318 #define MAX_REAL_LONG_REG 0
319
320 #endif /* x86_64 */
321
322 /* -----------------------------------------------------------------------------
323 The Motorola 680x0 register mapping
324
325 A Sun3 (mc680x0) has eight address registers, \tr{a0} to \tr{a7}, and
326 eight data registers, \tr{d0} to \tr{d7}. Address operations have to
327 be done through address registers; data registers are used for
328 comparison values and data.
329
330 Here's the register-usage picture for m68k boxes with GCC.
331
332 \begin{tabular}{ll}
333 a0 & used directly by GCC \\
334 a1 & used directly by GCC \\
335 \\
336 a2..a5 & callee-saved: available for STG registers \\
337 & (a5 may be special, ``global'' register for PIC?) \\
338 \\
339 a6 & C-stack frame pointer \\
340 a7 & C-stack pointer \\
341 \\
342 d0 & used directly by GCC \\
343 d1 & used directly by GCC \\
344 d2 & really needed for local optimisation by GCC \\
345 \\
346 d3..d7 & callee-saved: available for STG registers
347 \\
348 fp0 & call-clobbered \\
349 fp1 & call-clobbered \\
350 fp2..fp7 & callee-saved: available for STG registers
351 \end{tabular}
352 -------------------------------------------------------------------------- */
353
354 #if m68k_REGS
355
356 #define REG(x) __asm__(#x)
357
358 #define REG_Base a2
359
360 #define REG_Sp a3
361 #define REG_SpLim d3
362
363 #define REG_Hp d4
364 #define REG_HpLim d5
365
366 #define REG_R1 a5
367 #define REG_R2 d6
368 #define MAX_REAL_VANILLA_REG 2
369
370 #define REG_Ret d7
371
372 #define REG_F1 fp2
373 #define REG_F2 fp3
374 #define REG_F3 fp4
375 #define REG_F4 fp5
376
377 #define REG_D1 fp6
378 #define REG_D2 fp7
379
380 #endif /* m68k */
381
382 /* -----------------------------------------------------------------------------
383 The DECstation (MIPS) register mapping
384
385 Here's at least some simple stuff about registers on a MIPS.
386
387 \tr{s0}--\tr{s7} are callee-save integer registers; they are our
388 ``prize'' stolen registers. There is also a wad of callee-save
389 floating-point registers, \tr{$f20}--\tr{$f31}; we'll use some of
390 those.
391
392 \tr{t0}--\tr{t9} are caller-save (``temporary?'') integer registers.
393 We can steal some, but we might have to save/restore around ccalls.
394 -------------------------------------------------------------------------- */
395
396 #if mips_REGS
397
398 #define REG(x) __asm__("$" #x)
399
400 #define CALLER_SAVES_R5
401 #define CALLER_SAVES_R6
402 #define CALLER_SAVES_R7
403 #define CALLER_SAVES_R8
404
405 #define CALLER_SAVES_USER
406
407 #define REG_R1 16
408 #define REG_R2 17
409 #define REG_R3 18
410 #define REG_R4 19
411 #define REG_R5 12
412 #define REG_R6 13
413 #define REG_R7 14
414 #define REG_R8 15
415
416 #define REG_F1 f20
417 #define REG_F2 f22
418 #define REG_F3 f24
419 #define REG_F4 f26
420
421 #define REG_D1 f28
422 #define REG_D2 f30
423
424 #define REG_Sp 20
425 #define REG_SpLim 21
426
427 #define REG_Hp 22
428 #define REG_HpLim 23
429
430 #define REG_Base 30
431
432 #endif /* mipse[lb] */
433
434 /* -----------------------------------------------------------------------------
435 The PowerPC register mapping
436
437 0 system glue? (caller-save, volatile)
438 1 SP (callee-save, non-volatile)
439 2 AIX, powerpc64-linux:
440 RTOC (a strange special case)
441 darwin:
442 (caller-save, volatile)
443 powerpc32-linux:
444 reserved for use by system
445
446 3-10 args/return (caller-save, volatile)
447 11,12 system glue? (caller-save, volatile)
448 13 on 64-bit: reserved for thread state pointer
449 on 32-bit: (callee-save, non-volatile)
450 14-31 (callee-save, non-volatile)
451
452 f0 (caller-save, volatile)
453 f1-f13 args/return (caller-save, volatile)
454 f14-f31 (callee-save, non-volatile)
455
456 \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes.
457 \tr{0}--\tr{12} are caller-save registers.
458
459 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
460
461 We can do the Whole Business with callee-save registers only!
462 -------------------------------------------------------------------------- */
463
464 #if powerpc_REGS
465
466 #define REG(x) __asm__(#x)
467
468 #define REG_R1 r14
469 #define REG_R2 r15
470 #define REG_R3 r16
471 #define REG_R4 r17
472 #define REG_R5 r18
473 #define REG_R6 r19
474 #define REG_R7 r20
475 #define REG_R8 r21
476
477 #if darwin_REGS
478
479 #define REG_F1 f14
480 #define REG_F2 f15
481 #define REG_F3 f16
482 #define REG_F4 f17
483
484 #define REG_D1 f18
485 #define REG_D2 f19
486
487 #else
488
489 #define REG_F1 fr14
490 #define REG_F2 fr15
491 #define REG_F3 fr16
492 #define REG_F4 fr17
493
494 #define REG_D1 fr18
495 #define REG_D2 fr19
496
497 #endif
498
499 #define REG_Sp r22
500 #define REG_SpLim r24
501
502 #define REG_Hp r25
503 #define REG_HpLim r26
504
505 #define REG_Base r27
506
507 #endif /* powerpc */
508
509 /* -----------------------------------------------------------------------------
510 The IA64 register mapping
511
512 We place the general registers in the locals area of the register stack,
513 so that the call mechanism takes care of saving them for us. We reserve
514 the first 16 for gcc's use - since gcc uses the highest used register to
515 determine the register stack frame size, this gives us a constant size
516 register stack frame.
517
518 \tr{f16-f32} are the callee-saved floating point registers.
519 -------------------------------------------------------------------------- */
520
521 #if ia64_REGS
522
523 #define REG(x) __asm__(#x)
524
525 #define REG_R1 loc16
526 #define REG_R2 loc17
527 #define REG_R3 loc18
528 #define REG_R4 loc19
529 #define REG_R5 loc20
530 #define REG_R6 loc21
531 #define REG_R7 loc22
532 #define REG_R8 loc23
533
534 #define REG_F1 f16
535 #define REG_F2 f17
536 #define REG_F3 f18
537 #define REG_F4 f19
538
539 #define REG_D1 f20
540 #define REG_D2 f21
541
542 #define REG_Sp loc24
543 #define REG_SpLim loc26
544
545 #define REG_Hp loc27
546 #define REG_HpLim loc28
547
548 #endif /* ia64 */
549
550 /* -----------------------------------------------------------------------------
551 The Sun SPARC register mapping
552
553 The SPARC register (window) story: Remember, within the Haskell
554 Threaded World, we essentially ``shut down'' the register-window
555 mechanism---the window doesn't move at all while in this World. It
556 *does* move, of course, if we call out to arbitrary~C...
557
558 The %i, %l, and %o registers (8 each) are the input, local, and
559 output registers visible in one register window. The 8 %g (global)
560 registers are visible all the time.
561
562 %o0..%o7 not available; can be zapped by callee
563 (%o6 is C-stack ptr; %o7 hold ret addrs)
564 %i0..%i7 available (except %i6 is used as frame ptr)
565 (and %i7 tends to have ret-addr-ish things)
566 %l0..%l7 available
567 %g0..%g4 not available; prone to stomping by division, etc.
568 %g5..%g7 not available; reserved for the OS
569
570 Note: %g3 is *definitely* clobbered in the builtin divide code (and
571 our save/restore machinery is NOT GOOD ENOUGH for that); discretion
572 being the better part of valor, we also don't take %g4.
573
574 The paired nature of the floating point registers causes complications for
575 the native code generator. For convenience, we pretend that the first 22
576 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
577 float (single) regs. The NCG acts accordingly. That means that the
578 following FP assignment is rather fragile, and should only be changed
579 with extreme care. The current scheme is:
580
581 %f0 /%f1 FP return from C
582 %f2 /%f3 D1
583 %f4 /%f5 D2
584 %f6 /%f7 ncg double spill tmp #1
585 %f8 /%f9 ncg double spill tmp #2
586 %f10/%f11 allocatable
587 %f12/%f13 allocatable
588 %f14/%f15 allocatable
589 %f16/%f17 allocatable
590 %f18/%f19 allocatable
591 %f20/%f21 allocatable
592
593 %f22 F1
594 %f23 F2
595 %f24 F3
596 %f25 F4
597 %f26 ncg single spill tmp #1
598 %f27 ncg single spill tmp #2
599 %f28 allocatable
600 %f29 allocatable
601 %f30 allocatable
602 %f31 allocatable
603
604 -------------------------------------------------------------------------- */
605
606 #if sparc_REGS
607
608 #define REG(x) __asm__("%" #x)
609
610 #define CALLER_SAVES_USER
611
612 #define CALLER_SAVES_F1
613 #define CALLER_SAVES_F2
614 #define CALLER_SAVES_F3
615 #define CALLER_SAVES_F4
616 #define CALLER_SAVES_D1
617 #define CALLER_SAVES_D2
618
619 #define REG_R1 l1
620 #define REG_R2 l2
621 #define REG_R3 l3
622 #define REG_R4 l4
623 #define REG_R5 l5
624 #define REG_R6 i5
625
626 #define REG_F1 f22
627 #define REG_F2 f23
628 #define REG_F3 f24
629 #define REG_F4 f25
630 #define REG_D1 f2
631 #define REG_D2 f4
632
633 #define REG_Sp i0
634 #define REG_SpLim i2
635
636 #define REG_Hp i3
637 #define REG_HpLim i4
638
639 #define REG_Base i1
640
641 #define NCG_SpillTmp_I1 g1
642 #define NCG_SpillTmp_I2 g2
643 #define NCG_SpillTmp_F1 f26
644 #define NCG_SpillTmp_F2 f27
645 #define NCG_SpillTmp_D1 f6
646 #define NCG_SpillTmp_D2 f8
647
648 #define NCG_FirstFloatReg f22
649
650 #endif /* sparc */
651
652 #endif /* NO_REGS */
653
654 /* -----------------------------------------------------------------------------
655 * These constants define how many stg registers will be used for
656 * passing arguments (and results, in the case of an unboxed-tuple
657 * return).
658 *
659 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
660 * highest STG register to occupy a real machine register, otherwise
661 * the calling conventions will needlessly shuffle data between the
662 * stack and memory-resident STG registers. We might occasionally
663 * set these macros to other values for testing, though.
664 *
665 * Registers above these values might still be used, for instance to
666 * communicate with PrimOps and RTS functions.
667 */
668
669 #ifndef MAX_REAL_VANILLA_REG
670 # if defined(REG_R8)
671 # define MAX_REAL_VANILLA_REG 8
672 # elif defined(REG_R7)
673 # define MAX_REAL_VANILLA_REG 7
674 # elif defined(REG_R6)
675 # define MAX_REAL_VANILLA_REG 6
676 # elif defined(REG_R5)
677 # define MAX_REAL_VANILLA_REG 5
678 # elif defined(REG_R4)
679 # define MAX_REAL_VANILLA_REG 4
680 # elif defined(REG_R3)
681 # define MAX_REAL_VANILLA_REG 3
682 # elif defined(REG_R2)
683 # define MAX_REAL_VANILLA_REG 2
684 # elif defined(REG_R1)
685 # define MAX_REAL_VANILLA_REG 1
686 # else
687 # define MAX_REAL_VANILLA_REG 0
688 # endif
689 #endif
690
691 #ifndef MAX_REAL_FLOAT_REG
692 # if defined(REG_F4)
693 # define MAX_REAL_FLOAT_REG 4
694 # elif defined(REG_F3)
695 # define MAX_REAL_FLOAT_REG 3
696 # elif defined(REG_F2)
697 # define MAX_REAL_FLOAT_REG 2
698 # elif defined(REG_F1)
699 # define MAX_REAL_FLOAT_REG 1
700 # else
701 # define MAX_REAL_FLOAT_REG 0
702 # endif
703 #endif
704
705 #ifndef MAX_REAL_DOUBLE_REG
706 # if defined(REG_D2)
707 # define MAX_REAL_DOUBLE_REG 2
708 # elif defined(REG_D1)
709 # define MAX_REAL_DOUBLE_REG 1
710 # else
711 # define MAX_REAL_DOUBLE_REG 0
712 # endif
713 #endif
714
715 #ifndef MAX_REAL_LONG_REG
716 # if defined(REG_L1)
717 # define MAX_REAL_LONG_REG 1
718 # else
719 # define MAX_REAL_LONG_REG 0
720 # endif
721 #endif
722
723 /* define NO_ARG_REGS if we have no argument registers at all (we can
724 * optimise certain code paths using this predicate).
725 */
726 #if MAX_REAL_VANILLA_REG < 2
727 #define NO_ARG_REGS
728 #else
729 #undef NO_ARG_REGS
730 #endif
731
732 #endif /* MACHREGS_H */