a73705110d93f5a5d6f8bfe216923753a7e5a4d8
[ghc.git] / includes / stg / MachRegs.h
1 /* -----------------------------------------------------------------------------
2 *
3 * (c) The GHC Team, 1998-2011
4 *
5 * Registers used in STG code. Might or might not correspond to
6 * actual machine registers.
7 *
8 * Do not #include this file directly: #include "Rts.h" instead.
9 *
10 * To understand the structure of the RTS headers, see the wiki:
11 * http://hackage.haskell.org/trac/ghc/wiki/Commentary/SourceTree/Includes
12 *
13 * ---------------------------------------------------------------------------*/
14
15 #ifndef MACHREGS_H
16 #define MACHREGS_H
17
18 /* This file is #included into Haskell code in the compiler: #defines
19 * only in here please.
20 */
21
22 /*
23 * Undefine these as a precaution: some of them were found to be
24 * defined by system headers on ARM/Linux.
25 */
26 #undef REG_R1
27 #undef REG_R2
28 #undef REG_R3
29 #undef REG_R4
30 #undef REG_R5
31 #undef REG_R6
32 #undef REG_R7
33 #undef REG_R8
34 #undef REG_R9
35 #undef REG_R10
36
37 /*
38 * Defining MACHREGS_NO_REGS to 1 causes no global registers to be used.
39 * MACHREGS_NO_REGS is typically controlled by NO_REGS, which is
40 * typically defined by GHC, via a command-line option passed to gcc,
41 * when the -funregisterised flag is given.
42 *
43 * NB. When MACHREGS_NO_REGS to 1, calling & return conventions may be
44 * different. For example, all function arguments will be passed on
45 * the stack, and components of an unboxed tuple will be returned on
46 * the stack rather than in registers.
47 */
48 #if MACHREGS_NO_REGS == 1
49
50 /* Nothing */
51
52 #elif MACHREGS_NO_REGS == 0
53
54 /* ----------------------------------------------------------------------------
55 Caller saves and callee-saves regs.
56
57 Caller-saves regs have to be saved around C-calls made from STG
58 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
59 is designated caller-saves in that machine's C calling convention.
60
61 As it stands, the only registers that are ever marked caller saves
62 are the RX, FX, DX and USER registers; as a result, if you
63 decide to caller save a system register (e.g. SP, HP, etc), note that
64 this code path is completely untested! -- EZY
65 -------------------------------------------------------------------------- */
66
67 /* -----------------------------------------------------------------------------
68 The x86 register mapping
69
70 Ok, we've only got 6 general purpose registers, a frame pointer and a
71 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
72 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
73 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
74
75 Reg STG-Reg
76 ---------------
77 ebx Base
78 ebp Sp
79 esi R1
80 edi Hp
81
82 Leaving SpLim out of the picture.
83 -------------------------------------------------------------------------- */
84
85 #if MACHREGS_i386
86
87 #define REG(x) __asm__("%" #x)
88
89 #ifndef not_doing_dynamic_linking
90 #define REG_Base ebx
91 #endif
92 #define REG_Sp ebp
93
94 #ifndef STOLEN_X86_REGS
95 #define STOLEN_X86_REGS 4
96 #endif
97
98 #if STOLEN_X86_REGS >= 3
99 # define REG_R1 esi
100 #endif
101
102 #if STOLEN_X86_REGS >= 4
103 # define REG_Hp edi
104 #endif
105
106 #define REG_XMM1 xmm0
107 #define REG_XMM2 xmm1
108 #define REG_XMM3 xmm2
109 #define REG_XMM4 xmm3
110
111 #define REG_YMM1 ymm0
112 #define REG_YMM2 ymm1
113 #define REG_YMM3 ymm2
114 #define REG_YMM4 ymm3
115
116 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
117 #define MAX_REAL_FLOAT_REG 0
118 #define MAX_REAL_DOUBLE_REG 0
119 #define MAX_REAL_LONG_REG 0
120 #define MAX_REAL_XMM_REG 4
121 #define MAX_REAL_YMM_REG 4
122
123 /* -----------------------------------------------------------------------------
124 The x86-64 register mapping
125
126 %rax caller-saves, don't steal this one
127 %rbx YES
128 %rcx arg reg, caller-saves
129 %rdx arg reg, caller-saves
130 %rsi arg reg, caller-saves
131 %rdi arg reg, caller-saves
132 %rbp YES (our *prime* register)
133 %rsp (unavailable - stack pointer)
134 %r8 arg reg, caller-saves
135 %r9 arg reg, caller-saves
136 %r10 caller-saves
137 %r11 caller-saves
138 %r12 YES
139 %r13 YES
140 %r14 YES
141 %r15 YES
142
143 %xmm0-7 arg regs, caller-saves
144 %xmm8-15 caller-saves
145
146 Use the caller-saves regs for Rn, because we don't always have to
147 save those (as opposed to Sp/Hp/SpLim etc. which always have to be
148 saved).
149
150 --------------------------------------------------------------------------- */
151
152 #elif MACHREGS_x86_64
153
154 #define REG(x) __asm__("%" #x)
155
156 #define REG_Base r13
157 #define REG_Sp rbp
158 #define REG_Hp r12
159 #define REG_R1 rbx
160 #define REG_R2 r14
161 #define REG_R3 rsi
162 #define REG_R4 rdi
163 #define REG_R5 r8
164 #define REG_R6 r9
165 #define REG_SpLim r15
166
167 #define REG_F1 xmm1
168 #define REG_F2 xmm2
169 #define REG_F3 xmm3
170 #define REG_F4 xmm4
171 #define REG_F5 xmm5
172 #define REG_F6 xmm6
173
174 #define REG_D1 xmm1
175 #define REG_D2 xmm2
176 #define REG_D3 xmm3
177 #define REG_D4 xmm4
178 #define REG_D5 xmm5
179 #define REG_D6 xmm6
180
181 #define REG_XMM1 xmm1
182 #define REG_XMM2 xmm2
183 #define REG_XMM3 xmm3
184 #define REG_XMM4 xmm4
185 #define REG_XMM5 xmm5
186 #define REG_XMM6 xmm6
187
188 #define REG_YMM1 ymm1
189 #define REG_YMM2 ymm2
190 #define REG_YMM3 ymm3
191 #define REG_YMM4 ymm4
192 #define REG_YMM5 ymm5
193 #define REG_YMM6 ymm6
194
195 #if !defined(mingw32_HOST_OS)
196 #define CALLER_SAVES_R3
197 #define CALLER_SAVES_R4
198 #endif
199 #define CALLER_SAVES_R5
200 #define CALLER_SAVES_R6
201
202 #define CALLER_SAVES_F1
203 #define CALLER_SAVES_F2
204 #define CALLER_SAVES_F3
205 #define CALLER_SAVES_F4
206 #define CALLER_SAVES_F5
207 #if !defined(mingw32_HOST_OS)
208 #define CALLER_SAVES_F6
209 #endif
210
211 #define CALLER_SAVES_D1
212 #define CALLER_SAVES_D2
213 #define CALLER_SAVES_D3
214 #define CALLER_SAVES_D4
215 #define CALLER_SAVES_D5
216 #if !defined(mingw32_HOST_OS)
217 #define CALLER_SAVES_D6
218 #endif
219
220 #define CALLER_SAVES_XMM1
221 #define CALLER_SAVES_XMM2
222 #define CALLER_SAVES_XMM3
223 #define CALLER_SAVES_XMM4
224 #define CALLER_SAVES_XMM5
225 #if !defined(mingw32_HOST_OS)
226 #define CALLER_SAVES_XMM6
227 #endif
228
229 #define CALLER_SAVES_YMM1
230 #define CALLER_SAVES_YMM2
231 #define CALLER_SAVES_YMM3
232 #define CALLER_SAVES_YMM4
233 #define CALLER_SAVES_YMM5
234 #if !defined(mingw32_HOST_OS)
235 #define CALLER_SAVES_YMM6
236 #endif
237
238 #define MAX_REAL_VANILLA_REG 6
239 #define MAX_REAL_FLOAT_REG 6
240 #define MAX_REAL_DOUBLE_REG 6
241 #define MAX_REAL_LONG_REG 0
242 #define MAX_REAL_XMM_REG 6
243 #define MAX_REAL_YMM_REG 6
244
245 /* -----------------------------------------------------------------------------
246 The PowerPC register mapping
247
248 0 system glue? (caller-save, volatile)
249 1 SP (callee-save, non-volatile)
250 2 AIX, powerpc64-linux:
251 RTOC (a strange special case)
252 darwin:
253 (caller-save, volatile)
254 powerpc32-linux:
255 reserved for use by system
256
257 3-10 args/return (caller-save, volatile)
258 11,12 system glue? (caller-save, volatile)
259 13 on 64-bit: reserved for thread state pointer
260 on 32-bit: (callee-save, non-volatile)
261 14-31 (callee-save, non-volatile)
262
263 f0 (caller-save, volatile)
264 f1-f13 args/return (caller-save, volatile)
265 f14-f31 (callee-save, non-volatile)
266
267 \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes.
268 \tr{0}--\tr{12} are caller-save registers.
269
270 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
271
272 We can do the Whole Business with callee-save registers only!
273 -------------------------------------------------------------------------- */
274
275 #elif MACHREGS_powerpc
276
277 #define REG(x) __asm__(#x)
278
279 #define REG_R1 r14
280 #define REG_R2 r15
281 #define REG_R3 r16
282 #define REG_R4 r17
283 #define REG_R5 r18
284 #define REG_R6 r19
285 #define REG_R7 r20
286 #define REG_R8 r21
287
288 #if MACHREGS_darwin
289
290 #define REG_F1 f14
291 #define REG_F2 f15
292 #define REG_F3 f16
293 #define REG_F4 f17
294
295 #define REG_D1 f18
296 #define REG_D2 f19
297
298 #else
299
300 #define REG_F1 fr14
301 #define REG_F2 fr15
302 #define REG_F3 fr16
303 #define REG_F4 fr17
304
305 #define REG_D1 fr18
306 #define REG_D2 fr19
307
308 #endif
309
310 #define REG_Sp r22
311 #define REG_SpLim r24
312
313 #define REG_Hp r25
314
315 #define REG_Base r27
316
317 /* -----------------------------------------------------------------------------
318 The Sun SPARC register mapping
319
320 !! IMPORTANT: if you change this register mapping you must also update
321 compiler/nativeGen/SPARC/Regs.hs. That file handles the
322 mapping for the NCG. This one only affects via-c code.
323
324 The SPARC register (window) story: Remember, within the Haskell
325 Threaded World, we essentially ``shut down'' the register-window
326 mechanism---the window doesn't move at all while in this World. It
327 *does* move, of course, if we call out to arbitrary~C...
328
329 The %i, %l, and %o registers (8 each) are the input, local, and
330 output registers visible in one register window. The 8 %g (global)
331 registers are visible all the time.
332
333 zero: always zero
334 scratch: volatile across C-fn calls. used by linker.
335 app: usable by application
336 system: reserved for system
337
338 alloc: allocated to in the register allocator, intra-closure only
339
340 GHC usage v8 ABI v9 ABI
341 Global
342 %g0 zero zero zero
343 %g1 alloc scratch scrach
344 %g2 alloc app app
345 %g3 alloc app app
346 %g4 alloc app scratch
347 %g5 system scratch
348 %g6 system system
349 %g7 system system
350
351 Output: can be zapped by callee
352 %o0-o5 alloc caller saves
353 %o6 C stack ptr
354 %o7 C ret addr
355
356 Local: maintained by register windowing mechanism
357 %l0 alloc
358 %l1 R1
359 %l2 R2
360 %l3 R3
361 %l4 R4
362 %l5 R5
363 %l6 alloc
364 %l7 alloc
365
366 Input
367 %i0 Sp
368 %i1 Base
369 %i2 SpLim
370 %i3 Hp
371 %i4 alloc
372 %i5 R6
373 %i6 C frame ptr
374 %i7 C ret addr
375
376 The paired nature of the floating point registers causes complications for
377 the native code generator. For convenience, we pretend that the first 22
378 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
379 float (single) regs. The NCG acts accordingly. That means that the
380 following FP assignment is rather fragile, and should only be changed
381 with extreme care. The current scheme is:
382
383 %f0 /%f1 FP return from C
384 %f2 /%f3 D1
385 %f4 /%f5 D2
386 %f6 /%f7 ncg double spill tmp #1
387 %f8 /%f9 ncg double spill tmp #2
388 %f10/%f11 allocatable
389 %f12/%f13 allocatable
390 %f14/%f15 allocatable
391 %f16/%f17 allocatable
392 %f18/%f19 allocatable
393 %f20/%f21 allocatable
394
395 %f22 F1
396 %f23 F2
397 %f24 F3
398 %f25 F4
399 %f26 ncg single spill tmp #1
400 %f27 ncg single spill tmp #2
401 %f28 allocatable
402 %f29 allocatable
403 %f30 allocatable
404 %f31 allocatable
405
406 -------------------------------------------------------------------------- */
407
408 #elif MACHREGS_sparc
409
410 #define REG(x) __asm__("%" #x)
411
412 #define CALLER_SAVES_USER
413
414 #define CALLER_SAVES_F1
415 #define CALLER_SAVES_F2
416 #define CALLER_SAVES_F3
417 #define CALLER_SAVES_F4
418 #define CALLER_SAVES_D1
419 #define CALLER_SAVES_D2
420
421 #define REG_R1 l1
422 #define REG_R2 l2
423 #define REG_R3 l3
424 #define REG_R4 l4
425 #define REG_R5 l5
426 #define REG_R6 i5
427
428 #define REG_F1 f22
429 #define REG_F2 f23
430 #define REG_F3 f24
431 #define REG_F4 f25
432
433 /* for each of the double arg regs,
434 Dn_2 is the high half. */
435
436 #define REG_D1 f2
437 #define REG_D1_2 f3
438
439 #define REG_D2 f4
440 #define REG_D2_2 f5
441
442 #define REG_Sp i0
443 #define REG_SpLim i2
444
445 #define REG_Hp i3
446
447 #define REG_Base i1
448
449 #define NCG_FirstFloatReg f22
450
451 /* -----------------------------------------------------------------------------
452 The ARM EABI register mapping
453
454 Here we consider ARM mode (i.e. 32bit isns)
455 and also CPU with full VFPv3 implementation
456
457 ARM registers (see Chapter 5.1 in ARM IHI 0042D)
458
459 r15 PC The Program Counter.
460 r14 LR The Link Register.
461 r13 SP The Stack Pointer.
462 r12 IP The Intra-Procedure-call scratch register.
463 r11 v8 Variable-register 8.
464 r10 v7 Variable-register 7.
465 r9 v6/SB/TR Platform register. The meaning of this register is
466 defined by the platform standard.
467 r8 v5 Variable-register 5.
468 r7 v4 Variable register 4.
469 r6 v3 Variable register 3.
470 r5 v2 Variable register 2.
471 r4 v1 Variable register 1.
472 r3 a4 Argument / scratch register 4.
473 r2 a3 Argument / scratch register 3.
474 r1 a2 Argument / result / scratch register 2.
475 r0 a1 Argument / result / scratch register 1.
476
477 VFPv2/VFPv3/NEON registers
478 s0-s15/d0-d7/q0-q3 Argument / result/ scratch registers
479 s16-s31/d8-d15/q4-q7 callee-saved registers (must be preserved across
480 subrutine calls)
481
482 VFPv3/NEON registers (added to the VFPv2 registers set)
483 d16-d31/q8-q15 Argument / result/ scratch registers
484 ----------------------------------------------------------------------------- */
485
486 #elif MACHREGS_arm
487
488 #define REG(x) __asm__(#x)
489
490 #define REG_Base r4
491 #define REG_Sp r5
492 #define REG_Hp r6
493 #define REG_R1 r7
494 #define REG_R2 r8
495 #define REG_R3 r9
496 #define REG_R4 r10
497 #define REG_SpLim r11
498
499 #if !defined(arm_HOST_ARCH_PRE_ARMv6)
500 /* d8 */
501 #define REG_F1 s16
502 #define REG_F2 s17
503 /* d9 */
504 #define REG_F3 s18
505 #define REG_F4 s19
506
507 #define REG_D1 d10
508 #define REG_D2 d11
509 #endif
510
511 #else
512
513 #error Cannot find platform to give register info for
514
515 #endif
516
517 #else
518
519 #error Bad MACHREGS_NO_REGS value
520
521 #endif
522
523 /* -----------------------------------------------------------------------------
524 * These constants define how many stg registers will be used for
525 * passing arguments (and results, in the case of an unboxed-tuple
526 * return).
527 *
528 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
529 * highest STG register to occupy a real machine register, otherwise
530 * the calling conventions will needlessly shuffle data between the
531 * stack and memory-resident STG registers. We might occasionally
532 * set these macros to other values for testing, though.
533 *
534 * Registers above these values might still be used, for instance to
535 * communicate with PrimOps and RTS functions.
536 */
537
538 #ifndef MAX_REAL_VANILLA_REG
539 # if defined(REG_R10)
540 # define MAX_REAL_VANILLA_REG 10
541 # elif defined(REG_R9)
542 # define MAX_REAL_VANILLA_REG 9
543 # elif defined(REG_R8)
544 # define MAX_REAL_VANILLA_REG 8
545 # elif defined(REG_R7)
546 # define MAX_REAL_VANILLA_REG 7
547 # elif defined(REG_R6)
548 # define MAX_REAL_VANILLA_REG 6
549 # elif defined(REG_R5)
550 # define MAX_REAL_VANILLA_REG 5
551 # elif defined(REG_R4)
552 # define MAX_REAL_VANILLA_REG 4
553 # elif defined(REG_R3)
554 # define MAX_REAL_VANILLA_REG 3
555 # elif defined(REG_R2)
556 # define MAX_REAL_VANILLA_REG 2
557 # elif defined(REG_R1)
558 # define MAX_REAL_VANILLA_REG 1
559 # else
560 # define MAX_REAL_VANILLA_REG 0
561 # endif
562 #endif
563
564 #ifndef MAX_REAL_FLOAT_REG
565 # if defined(REG_F4)
566 # define MAX_REAL_FLOAT_REG 4
567 # elif defined(REG_F3)
568 # define MAX_REAL_FLOAT_REG 3
569 # elif defined(REG_F2)
570 # define MAX_REAL_FLOAT_REG 2
571 # elif defined(REG_F1)
572 # define MAX_REAL_FLOAT_REG 1
573 # else
574 # define MAX_REAL_FLOAT_REG 0
575 # endif
576 #endif
577
578 #ifndef MAX_REAL_DOUBLE_REG
579 # if defined(REG_D2)
580 # define MAX_REAL_DOUBLE_REG 2
581 # elif defined(REG_D1)
582 # define MAX_REAL_DOUBLE_REG 1
583 # else
584 # define MAX_REAL_DOUBLE_REG 0
585 # endif
586 #endif
587
588 #ifndef MAX_REAL_LONG_REG
589 # if defined(REG_L1)
590 # define MAX_REAL_LONG_REG 1
591 # else
592 # define MAX_REAL_LONG_REG 0
593 # endif
594 #endif
595
596 #ifndef MAX_REAL_XMM_REG
597 # if defined(REG_XMM6)
598 # define MAX_REAL_XMM_REG 6
599 # elif defined(REG_XMM5)
600 # define MAX_REAL_XMM_REG 5
601 # elif defined(REG_XMM4)
602 # define MAX_REAL_XMM_REG 4
603 # elif defined(REG_XMM3)
604 # define MAX_REAL_XMM_REG 3
605 # elif defined(REG_XMM2)
606 # define MAX_REAL_XMM_REG 2
607 # elif defined(REG_XMM1)
608 # define MAX_REAL_XMM_REG 1
609 # else
610 # define MAX_REAL_XMM_REG 0
611 # endif
612 #endif
613
614 /* define NO_ARG_REGS if we have no argument registers at all (we can
615 * optimise certain code paths using this predicate).
616 */
617 #if MAX_REAL_VANILLA_REG < 2
618 #define NO_ARG_REGS
619 #else
620 #undef NO_ARG_REGS
621 #endif
622
623 #endif /* MACHREGS_H */