Enable new warning for fragile/incorrect CPP #if usage
[ghc.git] / includes / stg / MachRegs.h
1 /* -----------------------------------------------------------------------------
2 *
3 * (c) The GHC Team, 1998-2014
4 *
5 * Registers used in STG code. Might or might not correspond to
6 * actual machine registers.
7 *
8 * Do not #include this file directly: #include "Rts.h" instead.
9 *
10 * To understand the structure of the RTS headers, see the wiki:
11 * http://ghc.haskell.org/trac/ghc/wiki/Commentary/SourceTree/Includes
12 *
13 * ---------------------------------------------------------------------------*/
14
15 #ifndef MACHREGS_H
16 #define MACHREGS_H
17
18 /* This file is #included into Haskell code in the compiler: #defines
19 * only in here please.
20 */
21
22 /*
23 * Undefine these as a precaution: some of them were found to be
24 * defined by system headers on ARM/Linux.
25 */
26 #undef REG_R1
27 #undef REG_R2
28 #undef REG_R3
29 #undef REG_R4
30 #undef REG_R5
31 #undef REG_R6
32 #undef REG_R7
33 #undef REG_R8
34 #undef REG_R9
35 #undef REG_R10
36
37 /*
38 * Defining MACHREGS_NO_REGS to 1 causes no global registers to be used.
39 * MACHREGS_NO_REGS is typically controlled by NO_REGS, which is
40 * typically defined by GHC, via a command-line option passed to gcc,
41 * when the -funregisterised flag is given.
42 *
43 * NB. When MACHREGS_NO_REGS to 1, calling & return conventions may be
44 * different. For example, all function arguments will be passed on
45 * the stack, and components of an unboxed tuple will be returned on
46 * the stack rather than in registers.
47 */
48 #if MACHREGS_NO_REGS == 1
49
50 /* Nothing */
51
52 #elif MACHREGS_NO_REGS == 0
53
54 /* ----------------------------------------------------------------------------
55 Caller saves and callee-saves regs.
56
57 Caller-saves regs have to be saved around C-calls made from STG
58 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
59 is designated caller-saves in that machine's C calling convention.
60
61 As it stands, the only registers that are ever marked caller saves
62 are the RX, FX, DX and USER registers; as a result, if you
63 decide to caller save a system register (e.g. SP, HP, etc), note that
64 this code path is completely untested! -- EZY
65 -------------------------------------------------------------------------- */
66
67 /* -----------------------------------------------------------------------------
68 The x86 register mapping
69
70 Ok, we've only got 6 general purpose registers, a frame pointer and a
71 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
72 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
73 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
74
75 Reg STG-Reg
76 ---------------
77 ebx Base
78 ebp Sp
79 esi R1
80 edi Hp
81
82 Leaving SpLim out of the picture.
83 -------------------------------------------------------------------------- */
84
85 #ifdef MACHREGS_i386
86
87 #define REG(x) __asm__("%" #x)
88
89 #ifndef not_doing_dynamic_linking
90 #define REG_Base ebx
91 #endif
92 #define REG_Sp ebp
93
94 #ifndef STOLEN_X86_REGS
95 #define STOLEN_X86_REGS 4
96 #endif
97
98 #if STOLEN_X86_REGS >= 3
99 # define REG_R1 esi
100 #endif
101
102 #if STOLEN_X86_REGS >= 4
103 # define REG_Hp edi
104 #endif
105 #define REG_MachSp esp
106
107 #define REG_XMM1 xmm0
108 #define REG_XMM2 xmm1
109 #define REG_XMM3 xmm2
110 #define REG_XMM4 xmm3
111
112 #define REG_YMM1 ymm0
113 #define REG_YMM2 ymm1
114 #define REG_YMM3 ymm2
115 #define REG_YMM4 ymm3
116
117 #define REG_ZMM1 zmm0
118 #define REG_ZMM2 zmm1
119 #define REG_ZMM3 zmm2
120 #define REG_ZMM4 zmm3
121
122 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
123 #define MAX_REAL_FLOAT_REG 0
124 #define MAX_REAL_DOUBLE_REG 0
125 #define MAX_REAL_LONG_REG 0
126 #define MAX_REAL_XMM_REG 4
127 #define MAX_REAL_YMM_REG 4
128 #define MAX_REAL_ZMM_REG 4
129
130 /* -----------------------------------------------------------------------------
131 The x86-64 register mapping
132
133 %rax caller-saves, don't steal this one
134 %rbx YES
135 %rcx arg reg, caller-saves
136 %rdx arg reg, caller-saves
137 %rsi arg reg, caller-saves
138 %rdi arg reg, caller-saves
139 %rbp YES (our *prime* register)
140 %rsp (unavailable - stack pointer)
141 %r8 arg reg, caller-saves
142 %r9 arg reg, caller-saves
143 %r10 caller-saves
144 %r11 caller-saves
145 %r12 YES
146 %r13 YES
147 %r14 YES
148 %r15 YES
149
150 %xmm0-7 arg regs, caller-saves
151 %xmm8-15 caller-saves
152
153 Use the caller-saves regs for Rn, because we don't always have to
154 save those (as opposed to Sp/Hp/SpLim etc. which always have to be
155 saved).
156
157 --------------------------------------------------------------------------- */
158
159 #elif defined(MACHREGS_x86_64)
160
161 #define REG(x) __asm__("%" #x)
162
163 #define REG_Base r13
164 #define REG_Sp rbp
165 #define REG_Hp r12
166 #define REG_R1 rbx
167 #define REG_R2 r14
168 #define REG_R3 rsi
169 #define REG_R4 rdi
170 #define REG_R5 r8
171 #define REG_R6 r9
172 #define REG_SpLim r15
173 #define REG_MachSp rsp
174
175 /*
176 Map both Fn and Dn to register xmmn so that we can pass a function any
177 combination of up to six Float# or Double# arguments without touching
178 the stack. See Note [Overlapping global registers] for implications.
179 */
180
181 #define REG_F1 xmm1
182 #define REG_F2 xmm2
183 #define REG_F3 xmm3
184 #define REG_F4 xmm4
185 #define REG_F5 xmm5
186 #define REG_F6 xmm6
187
188 #define REG_D1 xmm1
189 #define REG_D2 xmm2
190 #define REG_D3 xmm3
191 #define REG_D4 xmm4
192 #define REG_D5 xmm5
193 #define REG_D6 xmm6
194
195 #define REG_XMM1 xmm1
196 #define REG_XMM2 xmm2
197 #define REG_XMM3 xmm3
198 #define REG_XMM4 xmm4
199 #define REG_XMM5 xmm5
200 #define REG_XMM6 xmm6
201
202 #define REG_YMM1 ymm1
203 #define REG_YMM2 ymm2
204 #define REG_YMM3 ymm3
205 #define REG_YMM4 ymm4
206 #define REG_YMM5 ymm5
207 #define REG_YMM6 ymm6
208
209 #define REG_ZMM1 zmm1
210 #define REG_ZMM2 zmm2
211 #define REG_ZMM3 zmm3
212 #define REG_ZMM4 zmm4
213 #define REG_ZMM5 zmm5
214 #define REG_ZMM6 zmm6
215
216 #if !defined(mingw32_HOST_OS)
217 #define CALLER_SAVES_R3
218 #define CALLER_SAVES_R4
219 #endif
220 #define CALLER_SAVES_R5
221 #define CALLER_SAVES_R6
222
223 #define CALLER_SAVES_F1
224 #define CALLER_SAVES_F2
225 #define CALLER_SAVES_F3
226 #define CALLER_SAVES_F4
227 #define CALLER_SAVES_F5
228 #if !defined(mingw32_HOST_OS)
229 #define CALLER_SAVES_F6
230 #endif
231
232 #define CALLER_SAVES_D1
233 #define CALLER_SAVES_D2
234 #define CALLER_SAVES_D3
235 #define CALLER_SAVES_D4
236 #define CALLER_SAVES_D5
237 #if !defined(mingw32_HOST_OS)
238 #define CALLER_SAVES_D6
239 #endif
240
241 #define CALLER_SAVES_XMM1
242 #define CALLER_SAVES_XMM2
243 #define CALLER_SAVES_XMM3
244 #define CALLER_SAVES_XMM4
245 #define CALLER_SAVES_XMM5
246 #if !defined(mingw32_HOST_OS)
247 #define CALLER_SAVES_XMM6
248 #endif
249
250 #define CALLER_SAVES_YMM1
251 #define CALLER_SAVES_YMM2
252 #define CALLER_SAVES_YMM3
253 #define CALLER_SAVES_YMM4
254 #define CALLER_SAVES_YMM5
255 #if !defined(mingw32_HOST_OS)
256 #define CALLER_SAVES_YMM6
257 #endif
258
259 #define CALLER_SAVES_ZMM1
260 #define CALLER_SAVES_ZMM2
261 #define CALLER_SAVES_ZMM3
262 #define CALLER_SAVES_ZMM4
263 #define CALLER_SAVES_ZMM5
264 #if !defined(mingw32_HOST_OS)
265 #define CALLER_SAVES_ZMM6
266 #endif
267
268 #define MAX_REAL_VANILLA_REG 6
269 #define MAX_REAL_FLOAT_REG 6
270 #define MAX_REAL_DOUBLE_REG 6
271 #define MAX_REAL_LONG_REG 0
272 #define MAX_REAL_XMM_REG 6
273 #define MAX_REAL_YMM_REG 6
274 #define MAX_REAL_ZMM_REG 6
275
276 /* -----------------------------------------------------------------------------
277 The PowerPC register mapping
278
279 0 system glue? (caller-save, volatile)
280 1 SP (callee-save, non-volatile)
281 2 AIX, powerpc64-linux:
282 RTOC (a strange special case)
283 darwin:
284 (caller-save, volatile)
285 powerpc32-linux:
286 reserved for use by system
287
288 3-10 args/return (caller-save, volatile)
289 11,12 system glue? (caller-save, volatile)
290 13 on 64-bit: reserved for thread state pointer
291 on 32-bit: (callee-save, non-volatile)
292 14-31 (callee-save, non-volatile)
293
294 f0 (caller-save, volatile)
295 f1-f13 args/return (caller-save, volatile)
296 f14-f31 (callee-save, non-volatile)
297
298 \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes.
299 \tr{0}--\tr{12} are caller-save registers.
300
301 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
302
303 We can do the Whole Business with callee-save registers only!
304 -------------------------------------------------------------------------- */
305
306 #elif defined(MACHREGS_powerpc)
307
308 #define REG(x) __asm__(#x)
309
310 #define REG_R1 r14
311 #define REG_R2 r15
312 #define REG_R3 r16
313 #define REG_R4 r17
314 #define REG_R5 r18
315 #define REG_R6 r19
316 #define REG_R7 r20
317 #define REG_R8 r21
318
319 #ifdef MACHREGS_darwin
320
321 #define REG_F1 f14
322 #define REG_F2 f15
323 #define REG_F3 f16
324 #define REG_F4 f17
325
326 #define REG_D1 f18
327 #define REG_D2 f19
328
329 #else
330
331 #define REG_F1 fr14
332 #define REG_F2 fr15
333 #define REG_F3 fr16
334 #define REG_F4 fr17
335 #define REG_F5 fr18
336 #define REG_F6 fr19
337
338 #define REG_D1 fr20
339 #define REG_D2 fr21
340 #define REG_D3 fr22
341 #define REG_D4 fr23
342 #define REG_D5 fr24
343 #define REG_D6 fr25
344
345 #endif
346
347 #define REG_Sp r22
348 #define REG_SpLim r24
349
350 #define REG_Hp r25
351
352 #define REG_Base r27
353
354 /* -----------------------------------------------------------------------------
355 The Sun SPARC register mapping
356
357 !! IMPORTANT: if you change this register mapping you must also update
358 compiler/nativeGen/SPARC/Regs.hs. That file handles the
359 mapping for the NCG. This one only affects via-c code.
360
361 The SPARC register (window) story: Remember, within the Haskell
362 Threaded World, we essentially ``shut down'' the register-window
363 mechanism---the window doesn't move at all while in this World. It
364 *does* move, of course, if we call out to arbitrary~C...
365
366 The %i, %l, and %o registers (8 each) are the input, local, and
367 output registers visible in one register window. The 8 %g (global)
368 registers are visible all the time.
369
370 zero: always zero
371 scratch: volatile across C-fn calls. used by linker.
372 app: usable by application
373 system: reserved for system
374
375 alloc: allocated to in the register allocator, intra-closure only
376
377 GHC usage v8 ABI v9 ABI
378 Global
379 %g0 zero zero zero
380 %g1 alloc scratch scrach
381 %g2 alloc app app
382 %g3 alloc app app
383 %g4 alloc app scratch
384 %g5 system scratch
385 %g6 system system
386 %g7 system system
387
388 Output: can be zapped by callee
389 %o0-o5 alloc caller saves
390 %o6 C stack ptr
391 %o7 C ret addr
392
393 Local: maintained by register windowing mechanism
394 %l0 alloc
395 %l1 R1
396 %l2 R2
397 %l3 R3
398 %l4 R4
399 %l5 R5
400 %l6 alloc
401 %l7 alloc
402
403 Input
404 %i0 Sp
405 %i1 Base
406 %i2 SpLim
407 %i3 Hp
408 %i4 alloc
409 %i5 R6
410 %i6 C frame ptr
411 %i7 C ret addr
412
413 The paired nature of the floating point registers causes complications for
414 the native code generator. For convenience, we pretend that the first 22
415 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
416 float (single) regs. The NCG acts accordingly. That means that the
417 following FP assignment is rather fragile, and should only be changed
418 with extreme care. The current scheme is:
419
420 %f0 /%f1 FP return from C
421 %f2 /%f3 D1
422 %f4 /%f5 D2
423 %f6 /%f7 ncg double spill tmp #1
424 %f8 /%f9 ncg double spill tmp #2
425 %f10/%f11 allocatable
426 %f12/%f13 allocatable
427 %f14/%f15 allocatable
428 %f16/%f17 allocatable
429 %f18/%f19 allocatable
430 %f20/%f21 allocatable
431
432 %f22 F1
433 %f23 F2
434 %f24 F3
435 %f25 F4
436 %f26 ncg single spill tmp #1
437 %f27 ncg single spill tmp #2
438 %f28 allocatable
439 %f29 allocatable
440 %f30 allocatable
441 %f31 allocatable
442
443 -------------------------------------------------------------------------- */
444
445 #elif defined(MACHREGS_sparc)
446
447 #define REG(x) __asm__("%" #x)
448
449 #define CALLER_SAVES_USER
450
451 #define CALLER_SAVES_F1
452 #define CALLER_SAVES_F2
453 #define CALLER_SAVES_F3
454 #define CALLER_SAVES_F4
455 #define CALLER_SAVES_D1
456 #define CALLER_SAVES_D2
457
458 #define REG_R1 l1
459 #define REG_R2 l2
460 #define REG_R3 l3
461 #define REG_R4 l4
462 #define REG_R5 l5
463 #define REG_R6 i5
464
465 #define REG_F1 f22
466 #define REG_F2 f23
467 #define REG_F3 f24
468 #define REG_F4 f25
469
470 /* for each of the double arg regs,
471 Dn_2 is the high half. */
472
473 #define REG_D1 f2
474 #define REG_D1_2 f3
475
476 #define REG_D2 f4
477 #define REG_D2_2 f5
478
479 #define REG_Sp i0
480 #define REG_SpLim i2
481
482 #define REG_Hp i3
483
484 #define REG_Base i1
485
486 #define NCG_FirstFloatReg f22
487
488 /* -----------------------------------------------------------------------------
489 The ARM EABI register mapping
490
491 Here we consider ARM mode (i.e. 32bit isns)
492 and also CPU with full VFPv3 implementation
493
494 ARM registers (see Chapter 5.1 in ARM IHI 0042D and
495 Section 9.2.2 in ARM Software Development Toolkit Reference Guide)
496
497 r15 PC The Program Counter.
498 r14 LR The Link Register.
499 r13 SP The Stack Pointer.
500 r12 IP The Intra-Procedure-call scratch register.
501 r11 v8/fp Variable-register 8.
502 r10 v7/sl Variable-register 7.
503 r9 v6/SB/TR Platform register. The meaning of this register is
504 defined by the platform standard.
505 r8 v5 Variable-register 5.
506 r7 v4 Variable register 4.
507 r6 v3 Variable register 3.
508 r5 v2 Variable register 2.
509 r4 v1 Variable register 1.
510 r3 a4 Argument / scratch register 4.
511 r2 a3 Argument / scratch register 3.
512 r1 a2 Argument / result / scratch register 2.
513 r0 a1 Argument / result / scratch register 1.
514
515 VFPv2/VFPv3/NEON registers
516 s0-s15/d0-d7/q0-q3 Argument / result/ scratch registers
517 s16-s31/d8-d15/q4-q7 callee-saved registers (must be preserved across
518 subroutine calls)
519
520 VFPv3/NEON registers (added to the VFPv2 registers set)
521 d16-d31/q8-q15 Argument / result/ scratch registers
522 ----------------------------------------------------------------------------- */
523
524 #elif defined(MACHREGS_arm)
525
526 #define REG(x) __asm__(#x)
527
528 #define REG_Base r4
529 #define REG_Sp r5
530 #define REG_Hp r6
531 #define REG_R1 r7
532 #define REG_R2 r8
533 #define REG_R3 r9
534 #define REG_R4 r10
535 #define REG_SpLim r11
536
537 #if !defined(arm_HOST_ARCH_PRE_ARMv6)
538 /* d8 */
539 #define REG_F1 s16
540 #define REG_F2 s17
541 /* d9 */
542 #define REG_F3 s18
543 #define REG_F4 s19
544
545 #define REG_D1 d10
546 #define REG_D2 d11
547 #endif
548
549 /* -----------------------------------------------------------------------------
550 The ARMv8/AArch64 ABI register mapping
551
552 The AArch64 provides 31 64-bit general purpose registers
553 and 32 128-bit SIMD/floating point registers.
554
555 General purpose registers (see Chapter 5.1.1 in ARM IHI 0055B)
556
557 Register | Special | Role in the procedure call standard
558 ---------+---------+------------------------------------
559 SP | | The Stack Pointer
560 r30 | LR | The Link Register
561 r29 | FP | The Frame Pointer
562 r19-r28 | | Callee-saved registers
563 r18 | | The Platform Register, if needed;
564 | | or temporary register
565 r17 | IP1 | The second intra-procedure-call temporary register
566 r16 | IP0 | The first intra-procedure-call scratch register
567 r9-r15 | | Temporary registers
568 r8 | | Indirect result location register
569 r0-r7 | | Parameter/result registers
570
571
572 FPU/SIMD registers
573
574 s/d/q/v0-v7 Argument / result/ scratch registers
575 s/d/q/v8-v15 callee-saved registers (must be preserved across subroutine calls,
576 but only bottom 64-bit value needs to be preserved)
577 s/d/q/v16-v31 temporary registers
578
579 ----------------------------------------------------------------------------- */
580
581 #elif defined(MACHREGS_aarch64)
582
583 #define REG(x) __asm__(#x)
584
585 #define REG_Base r19
586 #define REG_Sp r20
587 #define REG_Hp r21
588 #define REG_R1 r22
589 #define REG_R2 r23
590 #define REG_R3 r24
591 #define REG_R4 r25
592 #define REG_R5 r26
593 #define REG_R6 r27
594 #define REG_SpLim r28
595
596 #define REG_F1 s8
597 #define REG_F2 s9
598 #define REG_F3 s10
599 #define REG_F4 s11
600
601 #define REG_D1 d12
602 #define REG_D2 d13
603 #define REG_D3 d14
604 #define REG_D4 d15
605
606 #else
607
608 #error Cannot find platform to give register info for
609
610 #endif
611
612 #else
613
614 #error Bad MACHREGS_NO_REGS value
615
616 #endif
617
618 /* -----------------------------------------------------------------------------
619 * These constants define how many stg registers will be used for
620 * passing arguments (and results, in the case of an unboxed-tuple
621 * return).
622 *
623 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
624 * highest STG register to occupy a real machine register, otherwise
625 * the calling conventions will needlessly shuffle data between the
626 * stack and memory-resident STG registers. We might occasionally
627 * set these macros to other values for testing, though.
628 *
629 * Registers above these values might still be used, for instance to
630 * communicate with PrimOps and RTS functions.
631 */
632
633 #ifndef MAX_REAL_VANILLA_REG
634 # if defined(REG_R10)
635 # define MAX_REAL_VANILLA_REG 10
636 # elif defined(REG_R9)
637 # define MAX_REAL_VANILLA_REG 9
638 # elif defined(REG_R8)
639 # define MAX_REAL_VANILLA_REG 8
640 # elif defined(REG_R7)
641 # define MAX_REAL_VANILLA_REG 7
642 # elif defined(REG_R6)
643 # define MAX_REAL_VANILLA_REG 6
644 # elif defined(REG_R5)
645 # define MAX_REAL_VANILLA_REG 5
646 # elif defined(REG_R4)
647 # define MAX_REAL_VANILLA_REG 4
648 # elif defined(REG_R3)
649 # define MAX_REAL_VANILLA_REG 3
650 # elif defined(REG_R2)
651 # define MAX_REAL_VANILLA_REG 2
652 # elif defined(REG_R1)
653 # define MAX_REAL_VANILLA_REG 1
654 # else
655 # define MAX_REAL_VANILLA_REG 0
656 # endif
657 #endif
658
659 #ifndef MAX_REAL_FLOAT_REG
660 # if defined(REG_F4)
661 # define MAX_REAL_FLOAT_REG 4
662 # elif defined(REG_F3)
663 # define MAX_REAL_FLOAT_REG 3
664 # elif defined(REG_F2)
665 # define MAX_REAL_FLOAT_REG 2
666 # elif defined(REG_F1)
667 # define MAX_REAL_FLOAT_REG 1
668 # else
669 # define MAX_REAL_FLOAT_REG 0
670 # endif
671 #endif
672
673 #ifndef MAX_REAL_DOUBLE_REG
674 # if defined(REG_D2)
675 # define MAX_REAL_DOUBLE_REG 2
676 # elif defined(REG_D1)
677 # define MAX_REAL_DOUBLE_REG 1
678 # else
679 # define MAX_REAL_DOUBLE_REG 0
680 # endif
681 #endif
682
683 #ifndef MAX_REAL_LONG_REG
684 # if defined(REG_L1)
685 # define MAX_REAL_LONG_REG 1
686 # else
687 # define MAX_REAL_LONG_REG 0
688 # endif
689 #endif
690
691 #ifndef MAX_REAL_XMM_REG
692 # if defined(REG_XMM6)
693 # define MAX_REAL_XMM_REG 6
694 # elif defined(REG_XMM5)
695 # define MAX_REAL_XMM_REG 5
696 # elif defined(REG_XMM4)
697 # define MAX_REAL_XMM_REG 4
698 # elif defined(REG_XMM3)
699 # define MAX_REAL_XMM_REG 3
700 # elif defined(REG_XMM2)
701 # define MAX_REAL_XMM_REG 2
702 # elif defined(REG_XMM1)
703 # define MAX_REAL_XMM_REG 1
704 # else
705 # define MAX_REAL_XMM_REG 0
706 # endif
707 #endif
708
709 /* define NO_ARG_REGS if we have no argument registers at all (we can
710 * optimise certain code paths using this predicate).
711 */
712 #if MAX_REAL_VANILLA_REG < 2
713 #define NO_ARG_REGS
714 #else
715 #undef NO_ARG_REGS
716 #endif
717
718 #endif /* MACHREGS_H */