6dc81f63c197a1fa5f561dbf00ea3c6af274e0de
[ghc.git] / includes / stg / MachRegs.h
1 /* -----------------------------------------------------------------------------
2 *
3 * (c) The GHC Team, 1998-2011
4 *
5 * Registers used in STG code. Might or might not correspond to
6 * actual machine registers.
7 *
8 * Do not #include this file directly: #include "Rts.h" instead.
9 *
10 * To understand the structure of the RTS headers, see the wiki:
11 * http://hackage.haskell.org/trac/ghc/wiki/Commentary/SourceTree/Includes
12 *
13 * ---------------------------------------------------------------------------*/
14
15 #ifndef MACHREGS_H
16 #define MACHREGS_H
17
18 /* This file is #included into Haskell code in the compiler: #defines
19 * only in here please.
20 */
21
22 /*
23 * Undefine these as a precaution: some of them were found to be
24 * defined by system headers on ARM/Linux.
25 */
26 #undef REG_R1
27 #undef REG_R2
28 #undef REG_R3
29 #undef REG_R4
30 #undef REG_R5
31 #undef REG_R6
32 #undef REG_R7
33 #undef REG_R8
34 #undef REG_R9
35 #undef REG_R10
36
37 /*
38 * Defining MACHREGS_NO_REGS to 1 causes no global registers to be used.
39 * MACHREGS_NO_REGS is typically controlled by NO_REGS, which is
40 * typically defined by GHC, via a command-line option passed to gcc,
41 * when the -funregisterised flag is given.
42 *
43 * NB. When MACHREGS_NO_REGS to 1, calling & return conventions may be
44 * different. For example, all function arguments will be passed on
45 * the stack, and components of an unboxed tuple will be returned on
46 * the stack rather than in registers.
47 */
48 #if MACHREGS_NO_REGS == 1
49
50 /* Nothing */
51
52 #elif MACHREGS_NO_REGS == 0
53
54 /* ----------------------------------------------------------------------------
55 Caller saves and callee-saves regs.
56
57 Caller-saves regs have to be saved around C-calls made from STG
58 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
59 is designated caller-saves in that machine's C calling convention.
60
61 As it stands, the only registers that are ever marked caller saves
62 are the RX, FX, DX and USER registers; as a result, if you
63 decide to caller save a system register (e.g. SP, HP, etc), note that
64 this code path is completely untested! -- EZY
65 -------------------------------------------------------------------------- */
66
67 /* -----------------------------------------------------------------------------
68 The x86 register mapping
69
70 Ok, we've only got 6 general purpose registers, a frame pointer and a
71 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
72 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
73 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
74
75 Reg STG-Reg
76 ---------------
77 ebx Base
78 ebp Sp
79 esi R1
80 edi Hp
81
82 Leaving SpLim out of the picture.
83 -------------------------------------------------------------------------- */
84
85 #if MACHREGS_i386
86
87 #define REG(x) __asm__("%" #x)
88
89 #ifndef not_doing_dynamic_linking
90 #define REG_Base ebx
91 #endif
92 #define REG_Sp ebp
93
94 #ifndef STOLEN_X86_REGS
95 #define STOLEN_X86_REGS 4
96 #endif
97
98 #if STOLEN_X86_REGS >= 3
99 # define REG_R1 esi
100 #endif
101
102 #if STOLEN_X86_REGS >= 4
103 # define REG_Hp edi
104 #endif
105
106 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
107 #define MAX_REAL_FLOAT_REG 0
108 #define MAX_REAL_DOUBLE_REG 0
109 #define MAX_REAL_LONG_REG 0
110 #define MAX_REAL_SSE_REG 0
111
112 /* -----------------------------------------------------------------------------
113 The x86-64 register mapping
114
115 %rax caller-saves, don't steal this one
116 %rbx YES
117 %rcx arg reg, caller-saves
118 %rdx arg reg, caller-saves
119 %rsi arg reg, caller-saves
120 %rdi arg reg, caller-saves
121 %rbp YES (our *prime* register)
122 %rsp (unavailable - stack pointer)
123 %r8 arg reg, caller-saves
124 %r9 arg reg, caller-saves
125 %r10 caller-saves
126 %r11 caller-saves
127 %r12 YES
128 %r13 YES
129 %r14 YES
130 %r15 YES
131
132 %xmm0-7 arg regs, caller-saves
133 %xmm8-15 caller-saves
134
135 Use the caller-saves regs for Rn, because we don't always have to
136 save those (as opposed to Sp/Hp/SpLim etc. which always have to be
137 saved).
138
139 --------------------------------------------------------------------------- */
140
141 #elif MACHREGS_x86_64
142
143 #define REG(x) __asm__("%" #x)
144
145 #define REG_Base r13
146 #define REG_Sp rbp
147 #define REG_Hp r12
148 #define REG_R1 rbx
149 #define REG_R2 r14
150 #define REG_R3 rsi
151 #define REG_R4 rdi
152 #define REG_R5 r8
153 #define REG_R6 r9
154 #define REG_SpLim r15
155
156 #define REG_F1 xmm1
157 #define REG_F2 xmm2
158 #define REG_F3 xmm3
159 #define REG_F4 xmm4
160 #define REG_F5 xmm5
161 #define REG_F6 xmm6
162
163 #define REG_D1 xmm1
164 #define REG_D2 xmm2
165 #define REG_D3 xmm3
166 #define REG_D4 xmm4
167 #define REG_D5 xmm5
168 #define REG_D6 xmm6
169
170 #define REG_SSE1 xmm1
171 #define REG_SSE2 xmm2
172 #define REG_SSE3 xmm3
173 #define REG_SSE4 xmm4
174 #define REG_SSE5 xmm5
175 #define REG_SSE6 xmm6
176
177 #if !defined(mingw32_HOST_OS)
178 #define CALLER_SAVES_R3
179 #define CALLER_SAVES_R4
180 #endif
181 #define CALLER_SAVES_R5
182 #define CALLER_SAVES_R6
183
184 #define CALLER_SAVES_F1
185 #define CALLER_SAVES_F2
186 #define CALLER_SAVES_F3
187 #define CALLER_SAVES_F4
188 #define CALLER_SAVES_F5
189 #if !defined(mingw32_HOST_OS)
190 #define CALLER_SAVES_F6
191 #endif
192
193 #define CALLER_SAVES_D1
194 #define CALLER_SAVES_D2
195 #define CALLER_SAVES_D3
196 #define CALLER_SAVES_D4
197 #define CALLER_SAVES_D5
198 #if !defined(mingw32_HOST_OS)
199 #define CALLER_SAVES_D6
200 #endif
201
202 #define CALLER_SAVES_SSE1
203 #define CALLER_SAVES_SSE2
204 #define CALLER_SAVES_SSE3
205 #define CALLER_SAVES_SSE4
206 #define CALLER_SAVES_SSE5
207 #if !defined(mingw32_HOST_OS)
208 #define CALLER_SAVES_SSE6
209 #endif
210
211 #define MAX_REAL_VANILLA_REG 6
212 #define MAX_REAL_FLOAT_REG 6
213 #define MAX_REAL_DOUBLE_REG 6
214 #define MAX_REAL_LONG_REG 0
215 #define MAX_REAL_SSE_REG 6
216
217 /* -----------------------------------------------------------------------------
218 The PowerPC register mapping
219
220 0 system glue? (caller-save, volatile)
221 1 SP (callee-save, non-volatile)
222 2 AIX, powerpc64-linux:
223 RTOC (a strange special case)
224 darwin:
225 (caller-save, volatile)
226 powerpc32-linux:
227 reserved for use by system
228
229 3-10 args/return (caller-save, volatile)
230 11,12 system glue? (caller-save, volatile)
231 13 on 64-bit: reserved for thread state pointer
232 on 32-bit: (callee-save, non-volatile)
233 14-31 (callee-save, non-volatile)
234
235 f0 (caller-save, volatile)
236 f1-f13 args/return (caller-save, volatile)
237 f14-f31 (callee-save, non-volatile)
238
239 \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes.
240 \tr{0}--\tr{12} are caller-save registers.
241
242 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
243
244 We can do the Whole Business with callee-save registers only!
245 -------------------------------------------------------------------------- */
246
247 #elif MACHREGS_powerpc
248
249 #define REG(x) __asm__(#x)
250
251 #define REG_R1 r14
252 #define REG_R2 r15
253 #define REG_R3 r16
254 #define REG_R4 r17
255 #define REG_R5 r18
256 #define REG_R6 r19
257 #define REG_R7 r20
258 #define REG_R8 r21
259
260 #if MACHREGS_darwin
261
262 #define REG_F1 f14
263 #define REG_F2 f15
264 #define REG_F3 f16
265 #define REG_F4 f17
266
267 #define REG_D1 f18
268 #define REG_D2 f19
269
270 #else
271
272 #define REG_F1 fr14
273 #define REG_F2 fr15
274 #define REG_F3 fr16
275 #define REG_F4 fr17
276
277 #define REG_D1 fr18
278 #define REG_D2 fr19
279
280 #endif
281
282 #define REG_Sp r22
283 #define REG_SpLim r24
284
285 #define REG_Hp r25
286
287 #define REG_Base r27
288
289 /* -----------------------------------------------------------------------------
290 The Sun SPARC register mapping
291
292 !! IMPORTANT: if you change this register mapping you must also update
293 compiler/nativeGen/SPARC/Regs.hs. That file handles the
294 mapping for the NCG. This one only affects via-c code.
295
296 The SPARC register (window) story: Remember, within the Haskell
297 Threaded World, we essentially ``shut down'' the register-window
298 mechanism---the window doesn't move at all while in this World. It
299 *does* move, of course, if we call out to arbitrary~C...
300
301 The %i, %l, and %o registers (8 each) are the input, local, and
302 output registers visible in one register window. The 8 %g (global)
303 registers are visible all the time.
304
305 zero: always zero
306 scratch: volatile across C-fn calls. used by linker.
307 app: usable by application
308 system: reserved for system
309
310 alloc: allocated to in the register allocator, intra-closure only
311
312 GHC usage v8 ABI v9 ABI
313 Global
314 %g0 zero zero zero
315 %g1 alloc scratch scrach
316 %g2 alloc app app
317 %g3 alloc app app
318 %g4 alloc app scratch
319 %g5 system scratch
320 %g6 system system
321 %g7 system system
322
323 Output: can be zapped by callee
324 %o0-o5 alloc caller saves
325 %o6 C stack ptr
326 %o7 C ret addr
327
328 Local: maintained by register windowing mechanism
329 %l0 alloc
330 %l1 R1
331 %l2 R2
332 %l3 R3
333 %l4 R4
334 %l5 R5
335 %l6 alloc
336 %l7 alloc
337
338 Input
339 %i0 Sp
340 %i1 Base
341 %i2 SpLim
342 %i3 Hp
343 %i4 alloc
344 %i5 R6
345 %i6 C frame ptr
346 %i7 C ret addr
347
348 The paired nature of the floating point registers causes complications for
349 the native code generator. For convenience, we pretend that the first 22
350 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
351 float (single) regs. The NCG acts accordingly. That means that the
352 following FP assignment is rather fragile, and should only be changed
353 with extreme care. The current scheme is:
354
355 %f0 /%f1 FP return from C
356 %f2 /%f3 D1
357 %f4 /%f5 D2
358 %f6 /%f7 ncg double spill tmp #1
359 %f8 /%f9 ncg double spill tmp #2
360 %f10/%f11 allocatable
361 %f12/%f13 allocatable
362 %f14/%f15 allocatable
363 %f16/%f17 allocatable
364 %f18/%f19 allocatable
365 %f20/%f21 allocatable
366
367 %f22 F1
368 %f23 F2
369 %f24 F3
370 %f25 F4
371 %f26 ncg single spill tmp #1
372 %f27 ncg single spill tmp #2
373 %f28 allocatable
374 %f29 allocatable
375 %f30 allocatable
376 %f31 allocatable
377
378 -------------------------------------------------------------------------- */
379
380 #elif MACHREGS_sparc
381
382 #define REG(x) __asm__("%" #x)
383
384 #define CALLER_SAVES_USER
385
386 #define CALLER_SAVES_F1
387 #define CALLER_SAVES_F2
388 #define CALLER_SAVES_F3
389 #define CALLER_SAVES_F4
390 #define CALLER_SAVES_D1
391 #define CALLER_SAVES_D2
392
393 #define REG_R1 l1
394 #define REG_R2 l2
395 #define REG_R3 l3
396 #define REG_R4 l4
397 #define REG_R5 l5
398 #define REG_R6 i5
399
400 #define REG_F1 f22
401 #define REG_F2 f23
402 #define REG_F3 f24
403 #define REG_F4 f25
404
405 /* for each of the double arg regs,
406 Dn_2 is the high half. */
407
408 #define REG_D1 f2
409 #define REG_D1_2 f3
410
411 #define REG_D2 f4
412 #define REG_D2_2 f5
413
414 #define REG_Sp i0
415 #define REG_SpLim i2
416
417 #define REG_Hp i3
418
419 #define REG_Base i1
420
421 #define NCG_FirstFloatReg f22
422
423 /* -----------------------------------------------------------------------------
424 The ARM EABI register mapping
425
426 Here we consider ARM mode (i.e. 32bit isns)
427 and also CPU with full VFPv3 implementation
428
429 ARM registers (see Chapter 5.1 in ARM IHI 0042D)
430
431 r15 PC The Program Counter.
432 r14 LR The Link Register.
433 r13 SP The Stack Pointer.
434 r12 IP The Intra-Procedure-call scratch register.
435 r11 v8 Variable-register 8.
436 r10 v7 Variable-register 7.
437 r9 v6/SB/TR Platform register. The meaning of this register is
438 defined by the platform standard.
439 r8 v5 Variable-register 5.
440 r7 v4 Variable register 4.
441 r6 v3 Variable register 3.
442 r5 v2 Variable register 2.
443 r4 v1 Variable register 1.
444 r3 a4 Argument / scratch register 4.
445 r2 a3 Argument / scratch register 3.
446 r1 a2 Argument / result / scratch register 2.
447 r0 a1 Argument / result / scratch register 1.
448
449 VFPv2/VFPv3/NEON registers
450 s0-s15/d0-d7/q0-q3 Argument / result/ scratch registers
451 s16-s31/d8-d15/q4-q7 callee-saved registers (must be preserved across
452 subrutine calls)
453
454 VFPv3/NEON registers (added to the VFPv2 registers set)
455 d16-d31/q8-q15 Argument / result/ scratch registers
456 ----------------------------------------------------------------------------- */
457
458 #elif MACHREGS_arm
459
460 #define REG(x) __asm__(#x)
461
462 #define REG_Base r4
463 #define REG_Sp r5
464 #define REG_Hp r6
465 #define REG_R1 r7
466 #define REG_R2 r8
467 #define REG_R3 r9
468 #define REG_R4 r10
469 #define REG_SpLim r11
470
471 #if !defined(arm_HOST_ARCH_PRE_ARMv6)
472 /* d8 */
473 #define REG_F1 s16
474 #define REG_F2 s17
475 /* d9 */
476 #define REG_F3 s18
477 #define REG_F4 s19
478
479 #define REG_D1 d10
480 #define REG_D2 d11
481 #endif
482
483 #else
484
485 #error Cannot find platform to give register info for
486
487 #endif
488
489 #else
490
491 #error Bad MACHREGS_NO_REGS value
492
493 #endif
494
495 /* -----------------------------------------------------------------------------
496 * These constants define how many stg registers will be used for
497 * passing arguments (and results, in the case of an unboxed-tuple
498 * return).
499 *
500 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
501 * highest STG register to occupy a real machine register, otherwise
502 * the calling conventions will needlessly shuffle data between the
503 * stack and memory-resident STG registers. We might occasionally
504 * set these macros to other values for testing, though.
505 *
506 * Registers above these values might still be used, for instance to
507 * communicate with PrimOps and RTS functions.
508 */
509
510 #ifndef MAX_REAL_VANILLA_REG
511 # if defined(REG_R10)
512 # define MAX_REAL_VANILLA_REG 10
513 # elif defined(REG_R9)
514 # define MAX_REAL_VANILLA_REG 9
515 # elif defined(REG_R8)
516 # define MAX_REAL_VANILLA_REG 8
517 # elif defined(REG_R7)
518 # define MAX_REAL_VANILLA_REG 7
519 # elif defined(REG_R6)
520 # define MAX_REAL_VANILLA_REG 6
521 # elif defined(REG_R5)
522 # define MAX_REAL_VANILLA_REG 5
523 # elif defined(REG_R4)
524 # define MAX_REAL_VANILLA_REG 4
525 # elif defined(REG_R3)
526 # define MAX_REAL_VANILLA_REG 3
527 # elif defined(REG_R2)
528 # define MAX_REAL_VANILLA_REG 2
529 # elif defined(REG_R1)
530 # define MAX_REAL_VANILLA_REG 1
531 # else
532 # define MAX_REAL_VANILLA_REG 0
533 # endif
534 #endif
535
536 #ifndef MAX_REAL_FLOAT_REG
537 # if defined(REG_F4)
538 # define MAX_REAL_FLOAT_REG 4
539 # elif defined(REG_F3)
540 # define MAX_REAL_FLOAT_REG 3
541 # elif defined(REG_F2)
542 # define MAX_REAL_FLOAT_REG 2
543 # elif defined(REG_F1)
544 # define MAX_REAL_FLOAT_REG 1
545 # else
546 # define MAX_REAL_FLOAT_REG 0
547 # endif
548 #endif
549
550 #ifndef MAX_REAL_DOUBLE_REG
551 # if defined(REG_D2)
552 # define MAX_REAL_DOUBLE_REG 2
553 # elif defined(REG_D1)
554 # define MAX_REAL_DOUBLE_REG 1
555 # else
556 # define MAX_REAL_DOUBLE_REG 0
557 # endif
558 #endif
559
560 #ifndef MAX_REAL_LONG_REG
561 # if defined(REG_L1)
562 # define MAX_REAL_LONG_REG 1
563 # else
564 # define MAX_REAL_LONG_REG 0
565 # endif
566 #endif
567
568 #ifndef MAX_REAL_SSE_REG
569 # if defined(REG_SSE6)
570 # define MAX_REAL_SSE_REG 6
571 # elif defined(REG_SSE5)
572 # define MAX_REAL_SSE_REG 5
573 # elif defined(REG_SSE4)
574 # define MAX_REAL_SSE_REG 4
575 # elif defined(REG_SSE3)
576 # define MAX_REAL_SSE_REG 3
577 # elif defined(REG_SSE2)
578 # define MAX_REAL_SSE_REG 2
579 # elif defined(REG_SSE1)
580 # define MAX_REAL_SSE_REG 1
581 # else
582 # define MAX_REAL_SSE_REG 0
583 # endif
584 #endif
585
586 /* define NO_ARG_REGS if we have no argument registers at all (we can
587 * optimise certain code paths using this predicate).
588 */
589 #if MAX_REAL_VANILLA_REG < 2
590 #define NO_ARG_REGS
591 #else
592 #undef NO_ARG_REGS
593 #endif
594
595 #endif /* MACHREGS_H */