Add support for passing SSE vectors in registers.
[ghc.git] / includes / CodeGen.Platform.hs
1
2 import CmmExpr
3 import FastBool
4 #if !(MACHREGS_i386 || MACHREGS_x86_64 || MACHREGS_sparc || MACHREGS_powerpc)
5 import Panic
6 #endif
7 import Reg
8
9 #include "ghcautoconf.h"
10 #include "stg/MachRegs.h"
11
12 #if MACHREGS_i386 || MACHREGS_x86_64
13
14 # if MACHREGS_i386
15 # define eax 0
16 # define ebx 1
17 # define ecx 2
18 # define edx 3
19 # define esi 4
20 # define edi 5
21 # define ebp 6
22 # define esp 7
23 # endif
24
25 # if MACHREGS_x86_64
26 # define rax 0
27 # define rbx 1
28 # define rcx 2
29 # define rdx 3
30 # define rsi 4
31 # define rdi 5
32 # define rbp 6
33 # define rsp 7
34 # define r8 8
35 # define r9 9
36 # define r10 10
37 # define r11 11
38 # define r12 12
39 # define r13 13
40 # define r14 14
41 # define r15 15
42 # endif
43
44 # define fake0 16
45 # define fake1 17
46 # define fake2 18
47 # define fake3 19
48 # define fake4 20
49 # define fake5 21
50
51 # define xmm0 24
52 # define xmm1 25
53 # define xmm2 26
54 # define xmm3 27
55 # define xmm4 28
56 # define xmm5 29
57 # define xmm6 30
58 # define xmm7 31
59 # define xmm8 32
60 # define xmm9 33
61 # define xmm10 34
62 # define xmm11 35
63 # define xmm12 36
64 # define xmm13 37
65 # define xmm14 38
66 # define xmm15 39
67
68 #elif MACHREGS_powerpc
69
70 # define r0 0
71 # define r1 1
72 # define r2 2
73 # define r3 3
74 # define r4 4
75 # define r5 5
76 # define r6 6
77 # define r7 7
78 # define r8 8
79 # define r9 9
80 # define r10 10
81 # define r11 11
82 # define r12 12
83 # define r13 13
84 # define r14 14
85 # define r15 15
86 # define r16 16
87 # define r17 17
88 # define r18 18
89 # define r19 19
90 # define r20 20
91 # define r21 21
92 # define r22 22
93 # define r23 23
94 # define r24 24
95 # define r25 25
96 # define r26 26
97 # define r27 27
98 # define r28 28
99 # define r29 29
100 # define r30 30
101 # define r31 31
102
103 # if MACHREGS_darwin
104 # define f0 32
105 # define f1 33
106 # define f2 34
107 # define f3 35
108 # define f4 36
109 # define f5 37
110 # define f6 38
111 # define f7 39
112 # define f8 40
113 # define f9 41
114 # define f10 42
115 # define f11 43
116 # define f12 44
117 # define f13 45
118 # define f14 46
119 # define f15 47
120 # define f16 48
121 # define f17 49
122 # define f18 50
123 # define f19 51
124 # define f20 52
125 # define f21 53
126 # define f22 54
127 # define f23 55
128 # define f24 56
129 # define f25 57
130 # define f26 58
131 # define f27 59
132 # define f28 60
133 # define f29 61
134 # define f30 62
135 # define f31 63
136 # else
137 # define fr0 32
138 # define fr1 33
139 # define fr2 34
140 # define fr3 35
141 # define fr4 36
142 # define fr5 37
143 # define fr6 38
144 # define fr7 39
145 # define fr8 40
146 # define fr9 41
147 # define fr10 42
148 # define fr11 43
149 # define fr12 44
150 # define fr13 45
151 # define fr14 46
152 # define fr15 47
153 # define fr16 48
154 # define fr17 49
155 # define fr18 50
156 # define fr19 51
157 # define fr20 52
158 # define fr21 53
159 # define fr22 54
160 # define fr23 55
161 # define fr24 56
162 # define fr25 57
163 # define fr26 58
164 # define fr27 59
165 # define fr28 60
166 # define fr29 61
167 # define fr30 62
168 # define fr31 63
169 # endif
170
171 #elif MACHREGS_sparc
172
173 # define g0 0
174 # define g1 1
175 # define g2 2
176 # define g3 3
177 # define g4 4
178 # define g5 5
179 # define g6 6
180 # define g7 7
181
182 # define o0 8
183 # define o1 9
184 # define o2 10
185 # define o3 11
186 # define o4 12
187 # define o5 13
188 # define o6 14
189 # define o7 15
190
191 # define l0 16
192 # define l1 17
193 # define l2 18
194 # define l3 19
195 # define l4 20
196 # define l5 21
197 # define l6 22
198 # define l7 23
199
200 # define i0 24
201 # define i1 25
202 # define i2 26
203 # define i3 27
204 # define i4 28
205 # define i5 29
206 # define i6 30
207 # define i7 31
208
209 # define f0 32
210 # define f1 33
211 # define f2 34
212 # define f3 35
213 # define f4 36
214 # define f5 37
215 # define f6 38
216 # define f7 39
217 # define f8 40
218 # define f9 41
219 # define f10 42
220 # define f11 43
221 # define f12 44
222 # define f13 45
223 # define f14 46
224 # define f15 47
225 # define f16 48
226 # define f17 49
227 # define f18 50
228 # define f19 51
229 # define f20 52
230 # define f21 53
231 # define f22 54
232 # define f23 55
233 # define f24 56
234 # define f25 57
235 # define f26 58
236 # define f27 59
237 # define f28 60
238 # define f29 61
239 # define f30 62
240 # define f31 63
241
242 #endif
243
244 callerSaves :: GlobalReg -> Bool
245 #ifdef CALLER_SAVES_Base
246 callerSaves BaseReg = True
247 #endif
248 #ifdef CALLER_SAVES_R1
249 callerSaves (VanillaReg 1 _) = True
250 #endif
251 #ifdef CALLER_SAVES_R2
252 callerSaves (VanillaReg 2 _) = True
253 #endif
254 #ifdef CALLER_SAVES_R3
255 callerSaves (VanillaReg 3 _) = True
256 #endif
257 #ifdef CALLER_SAVES_R4
258 callerSaves (VanillaReg 4 _) = True
259 #endif
260 #ifdef CALLER_SAVES_R5
261 callerSaves (VanillaReg 5 _) = True
262 #endif
263 #ifdef CALLER_SAVES_R6
264 callerSaves (VanillaReg 6 _) = True
265 #endif
266 #ifdef CALLER_SAVES_R7
267 callerSaves (VanillaReg 7 _) = True
268 #endif
269 #ifdef CALLER_SAVES_R8
270 callerSaves (VanillaReg 8 _) = True
271 #endif
272 #ifdef CALLER_SAVES_R9
273 callerSaves (VanillaReg 9 _) = True
274 #endif
275 #ifdef CALLER_SAVES_R10
276 callerSaves (VanillaReg 10 _) = True
277 #endif
278 #ifdef CALLER_SAVES_F1
279 callerSaves (FloatReg 1) = True
280 #endif
281 #ifdef CALLER_SAVES_F2
282 callerSaves (FloatReg 2) = True
283 #endif
284 #ifdef CALLER_SAVES_F3
285 callerSaves (FloatReg 3) = True
286 #endif
287 #ifdef CALLER_SAVES_F4
288 callerSaves (FloatReg 4) = True
289 #endif
290 #ifdef CALLER_SAVES_F5
291 callerSaves (FloatReg 5) = True
292 #endif
293 #ifdef CALLER_SAVES_F6
294 callerSaves (FloatReg 6) = True
295 #endif
296 #ifdef CALLER_SAVES_D1
297 callerSaves (DoubleReg 1) = True
298 #endif
299 #ifdef CALLER_SAVES_D2
300 callerSaves (DoubleReg 2) = True
301 #endif
302 #ifdef CALLER_SAVES_D3
303 callerSaves (DoubleReg 3) = True
304 #endif
305 #ifdef CALLER_SAVES_D4
306 callerSaves (DoubleReg 4) = True
307 #endif
308 #ifdef CALLER_SAVES_D5
309 callerSaves (DoubleReg 5) = True
310 #endif
311 #ifdef CALLER_SAVES_D6
312 callerSaves (DoubleReg 6) = True
313 #endif
314 #ifdef CALLER_SAVES_L1
315 callerSaves (LongReg 1) = True
316 #endif
317 #ifdef CALLER_SAVES_Sp
318 callerSaves Sp = True
319 #endif
320 #ifdef CALLER_SAVES_SpLim
321 callerSaves SpLim = True
322 #endif
323 #ifdef CALLER_SAVES_Hp
324 callerSaves Hp = True
325 #endif
326 #ifdef CALLER_SAVES_HpLim
327 callerSaves HpLim = True
328 #endif
329 #ifdef CALLER_SAVES_CCCS
330 callerSaves CCCS = True
331 #endif
332 #ifdef CALLER_SAVES_CurrentTSO
333 callerSaves CurrentTSO = True
334 #endif
335 #ifdef CALLER_SAVES_CurrentNursery
336 callerSaves CurrentNursery = True
337 #endif
338 callerSaves _ = False
339
340 activeStgRegs :: [GlobalReg]
341 activeStgRegs = [
342 #ifdef REG_Base
343 BaseReg
344 #endif
345 #ifdef REG_Sp
346 ,Sp
347 #endif
348 #ifdef REG_Hp
349 ,Hp
350 #endif
351 #ifdef REG_R1
352 ,VanillaReg 1 VGcPtr
353 #endif
354 #ifdef REG_R2
355 ,VanillaReg 2 VGcPtr
356 #endif
357 #ifdef REG_R3
358 ,VanillaReg 3 VGcPtr
359 #endif
360 #ifdef REG_R4
361 ,VanillaReg 4 VGcPtr
362 #endif
363 #ifdef REG_R5
364 ,VanillaReg 5 VGcPtr
365 #endif
366 #ifdef REG_R6
367 ,VanillaReg 6 VGcPtr
368 #endif
369 #ifdef REG_R7
370 ,VanillaReg 7 VGcPtr
371 #endif
372 #ifdef REG_R8
373 ,VanillaReg 8 VGcPtr
374 #endif
375 #ifdef REG_R9
376 ,VanillaReg 9 VGcPtr
377 #endif
378 #ifdef REG_R10
379 ,VanillaReg 10 VGcPtr
380 #endif
381 #ifdef REG_SpLim
382 ,SpLim
383 #endif
384 #if MAX_REAL_SSE_REG != 0
385 #ifdef REG_F1
386 ,FloatReg 1
387 #endif
388 #ifdef REG_D1
389 ,DoubleReg 1
390 #endif
391 #ifdef REG_XMM1
392 ,XmmReg 1
393 #endif
394 #ifdef REG_F2
395 ,FloatReg 2
396 #endif
397 #ifdef REG_D2
398 ,DoubleReg 2
399 #endif
400 #ifdef REG_XMM2
401 ,XmmReg 2
402 #endif
403 #ifdef REG_F3
404 ,FloatReg 3
405 #endif
406 #ifdef REG_D3
407 ,DoubleReg 3
408 #endif
409 #ifdef REG_XMM3
410 ,XmmReg 3
411 #endif
412 #ifdef REG_F4
413 ,FloatReg 4
414 #endif
415 #ifdef REG_D4
416 ,DoubleReg 4
417 #endif
418 #ifdef REG_XMM4
419 ,XmmReg 4
420 #endif
421 #ifdef REG_F5
422 ,FloatReg 5
423 #endif
424 #ifdef REG_D5
425 ,DoubleReg 5
426 #endif
427 #ifdef REG_XMM5
428 ,XmmReg 5
429 #endif
430 #ifdef REG_F6
431 ,FloatReg 6
432 #endif
433 #ifdef REG_D6
434 ,DoubleReg 6
435 #endif
436 #ifdef REG_XMM6
437 ,XmmReg 6
438 #endif
439 #else /* MAX_REAL_SSE_REG == 0 */
440 #ifdef REG_F1
441 ,FloatReg 1
442 #endif
443 #ifdef REG_F2
444 ,FloatReg 2
445 #endif
446 #ifdef REG_F3
447 ,FloatReg 3
448 #endif
449 #ifdef REG_F4
450 ,FloatReg 4
451 #endif
452 #ifdef REG_F5
453 ,FloatReg 5
454 #endif
455 #ifdef REG_F6
456 ,FloatReg 6
457 #endif
458 #ifdef REG_D1
459 ,DoubleReg 1
460 #endif
461 #ifdef REG_D2
462 ,DoubleReg 2
463 #endif
464 #ifdef REG_D3
465 ,DoubleReg 3
466 #endif
467 #ifdef REG_D4
468 ,DoubleReg 4
469 #endif
470 #ifdef REG_D5
471 ,DoubleReg 5
472 #endif
473 #ifdef REG_D6
474 ,DoubleReg 6
475 #endif
476 #endif /* MAX_REAL_SSE_REG == 0 */
477 ]
478
479 haveRegBase :: Bool
480 #ifdef REG_Base
481 haveRegBase = True
482 #else
483 haveRegBase = False
484 #endif
485
486 -- | Returns 'Nothing' if this global register is not stored
487 -- in a real machine register, otherwise returns @'Just' reg@, where
488 -- reg is the machine register it is stored in.
489 globalRegMaybe :: GlobalReg -> Maybe RealReg
490 #if MACHREGS_i386 || MACHREGS_x86_64 || MACHREGS_sparc || MACHREGS_powerpc
491 # ifdef REG_Base
492 globalRegMaybe BaseReg = Just (RealRegSingle REG_Base)
493 # endif
494 # ifdef REG_R1
495 globalRegMaybe (VanillaReg 1 _) = Just (RealRegSingle REG_R1)
496 # endif
497 # ifdef REG_R2
498 globalRegMaybe (VanillaReg 2 _) = Just (RealRegSingle REG_R2)
499 # endif
500 # ifdef REG_R3
501 globalRegMaybe (VanillaReg 3 _) = Just (RealRegSingle REG_R3)
502 # endif
503 # ifdef REG_R4
504 globalRegMaybe (VanillaReg 4 _) = Just (RealRegSingle REG_R4)
505 # endif
506 # ifdef REG_R5
507 globalRegMaybe (VanillaReg 5 _) = Just (RealRegSingle REG_R5)
508 # endif
509 # ifdef REG_R6
510 globalRegMaybe (VanillaReg 6 _) = Just (RealRegSingle REG_R6)
511 # endif
512 # ifdef REG_R7
513 globalRegMaybe (VanillaReg 7 _) = Just (RealRegSingle REG_R7)
514 # endif
515 # ifdef REG_R8
516 globalRegMaybe (VanillaReg 8 _) = Just (RealRegSingle REG_R8)
517 # endif
518 # ifdef REG_R9
519 globalRegMaybe (VanillaReg 9 _) = Just (RealRegSingle REG_R9)
520 # endif
521 # ifdef REG_R10
522 globalRegMaybe (VanillaReg 10 _) = Just (RealRegSingle REG_R10)
523 # endif
524 # ifdef REG_F1
525 globalRegMaybe (FloatReg 1) = Just (RealRegSingle REG_F1)
526 # endif
527 # ifdef REG_F2
528 globalRegMaybe (FloatReg 2) = Just (RealRegSingle REG_F2)
529 # endif
530 # ifdef REG_F3
531 globalRegMaybe (FloatReg 3) = Just (RealRegSingle REG_F3)
532 # endif
533 # ifdef REG_F4
534 globalRegMaybe (FloatReg 4) = Just (RealRegSingle REG_F4)
535 # endif
536 # ifdef REG_F5
537 globalRegMaybe (FloatReg 5) = Just (RealRegSingle REG_F5)
538 # endif
539 # ifdef REG_F6
540 globalRegMaybe (FloatReg 6) = Just (RealRegSingle REG_F6)
541 # endif
542 # ifdef REG_D1
543 globalRegMaybe (DoubleReg 1) =
544 # if MACHREGS_sparc
545 Just (RealRegPair REG_D1 (REG_D1 + 1))
546 # else
547 Just (RealRegSingle REG_D1)
548 # endif
549 # endif
550 # ifdef REG_D2
551 globalRegMaybe (DoubleReg 2) =
552 # if MACHREGS_sparc
553 Just (RealRegPair REG_D2 (REG_D2 + 1))
554 # else
555 Just (RealRegSingle REG_D2)
556 # endif
557 # endif
558 # ifdef REG_D3
559 globalRegMaybe (DoubleReg 3) =
560 # if MACHREGS_sparc
561 Just (RealRegPair REG_D3 (REG_D3 + 1))
562 # else
563 Just (RealRegSingle REG_D3)
564 # endif
565 # endif
566 # ifdef REG_D4
567 globalRegMaybe (DoubleReg 4) =
568 # if MACHREGS_sparc
569 Just (RealRegPair REG_D4 (REG_D4 + 1))
570 # else
571 Just (RealRegSingle REG_D4)
572 # endif
573 # endif
574 # ifdef REG_D5
575 globalRegMaybe (DoubleReg 5) =
576 # if MACHREGS_sparc
577 Just (RealRegPair REG_D5 (REG_D5 + 1))
578 # else
579 Just (RealRegSingle REG_D5)
580 # endif
581 # endif
582 # ifdef REG_D6
583 globalRegMaybe (DoubleReg 6) =
584 # if MACHREGS_sparc
585 Just (RealRegPair REG_D6 (REG_D6 + 1))
586 # else
587 Just (RealRegSingle REG_D6)
588 # endif
589 # endif
590 #if MAX_REAL_SSE_REG != 0
591 globalRegMaybe (XmmReg 1) = Just (RealRegSingle REG_XMM1)
592 globalRegMaybe (XmmReg 2) = Just (RealRegSingle REG_XMM2)
593 globalRegMaybe (XmmReg 3) = Just (RealRegSingle REG_XMM3)
594 globalRegMaybe (XmmReg 4) = Just (RealRegSingle REG_XMM4)
595 globalRegMaybe (XmmReg 5) = Just (RealRegSingle REG_XMM5)
596 globalRegMaybe (XmmReg 6) = Just (RealRegSingle REG_XMM6)
597 # endif
598 # ifdef REG_Sp
599 globalRegMaybe Sp = Just (RealRegSingle REG_Sp)
600 # endif
601 # ifdef REG_Lng1
602 globalRegMaybe (LongReg 1) = Just (RealRegSingle REG_Lng1)
603 # endif
604 # ifdef REG_Lng2
605 globalRegMaybe (LongReg 2) = Just (RealRegSingle REG_Lng2)
606 # endif
607 # ifdef REG_SpLim
608 globalRegMaybe SpLim = Just (RealRegSingle REG_SpLim)
609 # endif
610 # ifdef REG_Hp
611 globalRegMaybe Hp = Just (RealRegSingle REG_Hp)
612 # endif
613 # ifdef REG_HpLim
614 globalRegMaybe HpLim = Just (RealRegSingle REG_HpLim)
615 # endif
616 # ifdef REG_CurrentTSO
617 globalRegMaybe CurrentTSO = Just (RealRegSingle REG_CurrentTSO)
618 # endif
619 # ifdef REG_CurrentNursery
620 globalRegMaybe CurrentNursery = Just (RealRegSingle REG_CurrentNursery)
621 # endif
622 globalRegMaybe _ = Nothing
623 #else
624 globalRegMaybe = panic "globalRegMaybe not defined for this platform"
625 #endif
626
627 freeReg :: RegNo -> FastBool
628
629 #if MACHREGS_i386 || MACHREGS_x86_64
630
631 # if MACHREGS_i386
632 freeReg esp = fastBool False -- %esp is the C stack pointer
633 freeReg esi = fastBool False -- Note [esi/edi not allocatable]
634 freeReg edi = fastBool False
635 # endif
636 # if MACHREGS_x86_64
637 freeReg rsp = fastBool False -- %rsp is the C stack pointer
638 # endif
639
640 {-
641 Note [esi/edi not allocatable]
642
643 %esi is mapped to R1, so %esi would normally be allocatable while it
644 is not being used for R1. However, %esi has no 8-bit version on x86,
645 and the linear register allocator is not sophisticated enough to
646 handle this irregularity (we need more RegClasses). The
647 graph-colouring allocator also cannot handle this - it was designed
648 with more flexibility in mind, but the current implementation is
649 restricted to the same set of classes as the linear allocator.
650
651 Hence, on x86 esi and edi are treated as not allocatable.
652 -}
653
654 -- split patterns in two functions to prevent overlaps
655 freeReg r = freeRegBase r
656
657 freeRegBase :: RegNo -> FastBool
658 # ifdef REG_Base
659 freeRegBase REG_Base = fastBool False
660 # endif
661 # ifdef REG_Sp
662 freeRegBase REG_Sp = fastBool False
663 # endif
664 # ifdef REG_SpLim
665 freeRegBase REG_SpLim = fastBool False
666 # endif
667 # ifdef REG_Hp
668 freeRegBase REG_Hp = fastBool False
669 # endif
670 # ifdef REG_HpLim
671 freeRegBase REG_HpLim = fastBool False
672 # endif
673 -- All other regs are considered to be "free", because we can track
674 -- their liveness accurately.
675 freeRegBase _ = fastBool True
676
677 #elif MACHREGS_powerpc
678
679 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns,
680 -- but it's actually free
681 freeReg 1 = fastBool False -- The Stack Pointer
682 # if !MACHREGS_darwin
683 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
684 freeReg 2 = fastBool False
685 # endif
686 # ifdef REG_Base
687 freeReg REG_Base = fastBool False
688 # endif
689 # ifdef REG_R1
690 freeReg REG_R1 = fastBool False
691 # endif
692 # ifdef REG_R2
693 freeReg REG_R2 = fastBool False
694 # endif
695 # ifdef REG_R3
696 freeReg REG_R3 = fastBool False
697 # endif
698 # ifdef REG_R4
699 freeReg REG_R4 = fastBool False
700 # endif
701 # ifdef REG_R5
702 freeReg REG_R5 = fastBool False
703 # endif
704 # ifdef REG_R6
705 freeReg REG_R6 = fastBool False
706 # endif
707 # ifdef REG_R7
708 freeReg REG_R7 = fastBool False
709 # endif
710 # ifdef REG_R8
711 freeReg REG_R8 = fastBool False
712 # endif
713 # ifdef REG_R9
714 freeReg REG_R9 = fastBool False
715 # endif
716 # ifdef REG_R10
717 freeReg REG_R10 = fastBool False
718 # endif
719 # ifdef REG_F1
720 freeReg REG_F1 = fastBool False
721 # endif
722 # ifdef REG_F2
723 freeReg REG_F2 = fastBool False
724 # endif
725 # ifdef REG_F3
726 freeReg REG_F3 = fastBool False
727 # endif
728 # ifdef REG_F4
729 freeReg REG_F4 = fastBool False
730 # endif
731 # ifdef REG_F5
732 freeReg REG_F5 = fastBool False
733 # endif
734 # ifdef REG_F6
735 freeReg REG_F6 = fastBool False
736 # endif
737 # ifdef REG_D1
738 freeReg REG_D1 = fastBool False
739 # endif
740 # ifdef REG_D2
741 freeReg REG_D2 = fastBool False
742 # endif
743 # ifdef REG_D3
744 freeReg REG_D3 = fastBool False
745 # endif
746 # ifdef REG_D4
747 freeReg REG_D4 = fastBool False
748 # endif
749 # ifdef REG_D5
750 freeReg REG_D5 = fastBool False
751 # endif
752 # ifdef REG_D6
753 freeReg REG_D6 = fastBool False
754 # endif
755 # ifdef REG_Sp
756 freeReg REG_Sp = fastBool False
757 # endif
758 # ifdef REG_Su
759 freeReg REG_Su = fastBool False
760 # endif
761 # ifdef REG_SpLim
762 freeReg REG_SpLim = fastBool False
763 # endif
764 # ifdef REG_Hp
765 freeReg REG_Hp = fastBool False
766 # endif
767 # ifdef REG_HpLim
768 freeReg REG_HpLim = fastBool False
769 # endif
770 freeReg _ = fastBool True
771
772 #elif MACHREGS_sparc
773
774 -- SPARC regs used by the OS / ABI
775 -- %g0(r0) is always zero
776 freeReg g0 = fastBool False
777
778 -- %g5(r5) - %g7(r7)
779 -- are reserved for the OS
780 freeReg g5 = fastBool False
781 freeReg g6 = fastBool False
782 freeReg g7 = fastBool False
783
784 -- %o6(r14)
785 -- is the C stack pointer
786 freeReg o6 = fastBool False
787
788 -- %o7(r15)
789 -- holds the C return address
790 freeReg o7 = fastBool False
791
792 -- %i6(r30)
793 -- is the C frame pointer
794 freeReg i6 = fastBool False
795
796 -- %i7(r31)
797 -- is used for C return addresses
798 freeReg i7 = fastBool False
799
800 -- %f0(r32) - %f1(r32)
801 -- are C floating point return regs
802 freeReg f0 = fastBool False
803 freeReg f1 = fastBool False
804
805 {-
806 freeReg regNo
807 -- don't release high half of double regs
808 | regNo >= f0
809 , regNo < NCG_FirstFloatReg
810 , regNo `mod` 2 /= 0
811 = fastBool False
812 -}
813
814 # ifdef REG_Base
815 freeReg REG_Base = fastBool False
816 # endif
817 # ifdef REG_R1
818 freeReg REG_R1 = fastBool False
819 # endif
820 # ifdef REG_R2
821 freeReg REG_R2 = fastBool False
822 # endif
823 # ifdef REG_R3
824 freeReg REG_R3 = fastBool False
825 # endif
826 # ifdef REG_R4
827 freeReg REG_R4 = fastBool False
828 # endif
829 # ifdef REG_R5
830 freeReg REG_R5 = fastBool False
831 # endif
832 # ifdef REG_R6
833 freeReg REG_R6 = fastBool False
834 # endif
835 # ifdef REG_R7
836 freeReg REG_R7 = fastBool False
837 # endif
838 # ifdef REG_R8
839 freeReg REG_R8 = fastBool False
840 # endif
841 # ifdef REG_R9
842 freeReg REG_R9 = fastBool False
843 # endif
844 # ifdef REG_R10
845 freeReg REG_R10 = fastBool False
846 # endif
847 # ifdef REG_F1
848 freeReg REG_F1 = fastBool False
849 # endif
850 # ifdef REG_F2
851 freeReg REG_F2 = fastBool False
852 # endif
853 # ifdef REG_F3
854 freeReg REG_F3 = fastBool False
855 # endif
856 # ifdef REG_F4
857 freeReg REG_F4 = fastBool False
858 # endif
859 # ifdef REG_F5
860 freeReg REG_F5 = fastBool False
861 # endif
862 # ifdef REG_F6
863 freeReg REG_F6 = fastBool False
864 # endif
865 # ifdef REG_D1
866 freeReg REG_D1 = fastBool False
867 # endif
868 # ifdef REG_D1_2
869 freeReg REG_D1_2 = fastBool False
870 # endif
871 # ifdef REG_D2
872 freeReg REG_D2 = fastBool False
873 # endif
874 # ifdef REG_D2_2
875 freeReg REG_D2_2 = fastBool False
876 # endif
877 # ifdef REG_D3
878 freeReg REG_D3 = fastBool False
879 # endif
880 # ifdef REG_D3_2
881 freeReg REG_D3_2 = fastBool False
882 # endif
883 # ifdef REG_D4
884 freeReg REG_D4 = fastBool False
885 # endif
886 # ifdef REG_D4_2
887 freeReg REG_D4_2 = fastBool False
888 # endif
889 # ifdef REG_D5
890 freeReg REG_D5 = fastBool False
891 # endif
892 # ifdef REG_D5_2
893 freeReg REG_D5_2 = fastBool False
894 # endif
895 # ifdef REG_D6
896 freeReg REG_D6 = fastBool False
897 # endif
898 # ifdef REG_D6_2
899 freeReg REG_D6_2 = fastBool False
900 # endif
901 # ifdef REG_Sp
902 freeReg REG_Sp = fastBool False
903 # endif
904 # ifdef REG_Su
905 freeReg REG_Su = fastBool False
906 # endif
907 # ifdef REG_SpLim
908 freeReg REG_SpLim = fastBool False
909 # endif
910 # ifdef REG_Hp
911 freeReg REG_Hp = fastBool False
912 # endif
913 # ifdef REG_HpLim
914 freeReg REG_HpLim = fastBool False
915 # endif
916 freeReg _ = fastBool True
917
918 #else
919
920 freeReg = panic "freeReg not defined for this platform"
921
922 #endif
923