Fold integer-simple.git into ghc.git (re #8545)
[ghc.git] / includes / stg / MachRegs.h
1 /* -----------------------------------------------------------------------------
2 *
3 * (c) The GHC Team, 1998-2011
4 *
5 * Registers used in STG code. Might or might not correspond to
6 * actual machine registers.
7 *
8 * Do not #include this file directly: #include "Rts.h" instead.
9 *
10 * To understand the structure of the RTS headers, see the wiki:
11 * http://ghc.haskell.org/trac/ghc/wiki/Commentary/SourceTree/Includes
12 *
13 * ---------------------------------------------------------------------------*/
14
15 #ifndef MACHREGS_H
16 #define MACHREGS_H
17
18 /* This file is #included into Haskell code in the compiler: #defines
19 * only in here please.
20 */
21
22 /*
23 * Undefine these as a precaution: some of them were found to be
24 * defined by system headers on ARM/Linux.
25 */
26 #undef REG_R1
27 #undef REG_R2
28 #undef REG_R3
29 #undef REG_R4
30 #undef REG_R5
31 #undef REG_R6
32 #undef REG_R7
33 #undef REG_R8
34 #undef REG_R9
35 #undef REG_R10
36
37 /*
38 * Defining MACHREGS_NO_REGS to 1 causes no global registers to be used.
39 * MACHREGS_NO_REGS is typically controlled by NO_REGS, which is
40 * typically defined by GHC, via a command-line option passed to gcc,
41 * when the -funregisterised flag is given.
42 *
43 * NB. When MACHREGS_NO_REGS to 1, calling & return conventions may be
44 * different. For example, all function arguments will be passed on
45 * the stack, and components of an unboxed tuple will be returned on
46 * the stack rather than in registers.
47 */
48 #if MACHREGS_NO_REGS == 1
49
50 /* Nothing */
51
52 #elif MACHREGS_NO_REGS == 0
53
54 /* ----------------------------------------------------------------------------
55 Caller saves and callee-saves regs.
56
57 Caller-saves regs have to be saved around C-calls made from STG
58 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
59 is designated caller-saves in that machine's C calling convention.
60
61 As it stands, the only registers that are ever marked caller saves
62 are the RX, FX, DX and USER registers; as a result, if you
63 decide to caller save a system register (e.g. SP, HP, etc), note that
64 this code path is completely untested! -- EZY
65 -------------------------------------------------------------------------- */
66
67 /* -----------------------------------------------------------------------------
68 The x86 register mapping
69
70 Ok, we've only got 6 general purpose registers, a frame pointer and a
71 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
72 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
73 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
74
75 Reg STG-Reg
76 ---------------
77 ebx Base
78 ebp Sp
79 esi R1
80 edi Hp
81
82 Leaving SpLim out of the picture.
83 -------------------------------------------------------------------------- */
84
85 #if MACHREGS_i386
86
87 #define REG(x) __asm__("%" #x)
88
89 #ifndef not_doing_dynamic_linking
90 #define REG_Base ebx
91 #endif
92 #define REG_Sp ebp
93
94 #ifndef STOLEN_X86_REGS
95 #define STOLEN_X86_REGS 4
96 #endif
97
98 #if STOLEN_X86_REGS >= 3
99 # define REG_R1 esi
100 #endif
101
102 #if STOLEN_X86_REGS >= 4
103 # define REG_Hp edi
104 #endif
105
106 #define REG_XMM1 xmm0
107 #define REG_XMM2 xmm1
108 #define REG_XMM3 xmm2
109 #define REG_XMM4 xmm3
110
111 #define REG_YMM1 ymm0
112 #define REG_YMM2 ymm1
113 #define REG_YMM3 ymm2
114 #define REG_YMM4 ymm3
115
116 #define REG_ZMM1 zmm0
117 #define REG_ZMM2 zmm1
118 #define REG_ZMM3 zmm2
119 #define REG_ZMM4 zmm3
120
121 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
122 #define MAX_REAL_FLOAT_REG 0
123 #define MAX_REAL_DOUBLE_REG 0
124 #define MAX_REAL_LONG_REG 0
125 #define MAX_REAL_XMM_REG 4
126 #define MAX_REAL_YMM_REG 4
127 #define MAX_REAL_ZMM_REG 4
128
129 /* -----------------------------------------------------------------------------
130 The x86-64 register mapping
131
132 %rax caller-saves, don't steal this one
133 %rbx YES
134 %rcx arg reg, caller-saves
135 %rdx arg reg, caller-saves
136 %rsi arg reg, caller-saves
137 %rdi arg reg, caller-saves
138 %rbp YES (our *prime* register)
139 %rsp (unavailable - stack pointer)
140 %r8 arg reg, caller-saves
141 %r9 arg reg, caller-saves
142 %r10 caller-saves
143 %r11 caller-saves
144 %r12 YES
145 %r13 YES
146 %r14 YES
147 %r15 YES
148
149 %xmm0-7 arg regs, caller-saves
150 %xmm8-15 caller-saves
151
152 Use the caller-saves regs for Rn, because we don't always have to
153 save those (as opposed to Sp/Hp/SpLim etc. which always have to be
154 saved).
155
156 --------------------------------------------------------------------------- */
157
158 #elif MACHREGS_x86_64
159
160 #define REG(x) __asm__("%" #x)
161
162 #define REG_Base r13
163 #define REG_Sp rbp
164 #define REG_Hp r12
165 #define REG_R1 rbx
166 #define REG_R2 r14
167 #define REG_R3 rsi
168 #define REG_R4 rdi
169 #define REG_R5 r8
170 #define REG_R6 r9
171 #define REG_SpLim r15
172
173 #define REG_F1 xmm1
174 #define REG_F2 xmm2
175 #define REG_F3 xmm3
176 #define REG_F4 xmm4
177 #define REG_F5 xmm5
178 #define REG_F6 xmm6
179
180 #define REG_D1 xmm1
181 #define REG_D2 xmm2
182 #define REG_D3 xmm3
183 #define REG_D4 xmm4
184 #define REG_D5 xmm5
185 #define REG_D6 xmm6
186
187 #define REG_XMM1 xmm1
188 #define REG_XMM2 xmm2
189 #define REG_XMM3 xmm3
190 #define REG_XMM4 xmm4
191 #define REG_XMM5 xmm5
192 #define REG_XMM6 xmm6
193
194 #define REG_YMM1 ymm1
195 #define REG_YMM2 ymm2
196 #define REG_YMM3 ymm3
197 #define REG_YMM4 ymm4
198 #define REG_YMM5 ymm5
199 #define REG_YMM6 ymm6
200
201 #define REG_ZMM1 zmm1
202 #define REG_ZMM2 zmm2
203 #define REG_ZMM3 zmm3
204 #define REG_ZMM4 zmm4
205 #define REG_ZMM5 zmm5
206 #define REG_ZMM6 zmm6
207
208 #if !defined(mingw32_HOST_OS)
209 #define CALLER_SAVES_R3
210 #define CALLER_SAVES_R4
211 #endif
212 #define CALLER_SAVES_R5
213 #define CALLER_SAVES_R6
214
215 #define CALLER_SAVES_F1
216 #define CALLER_SAVES_F2
217 #define CALLER_SAVES_F3
218 #define CALLER_SAVES_F4
219 #define CALLER_SAVES_F5
220 #if !defined(mingw32_HOST_OS)
221 #define CALLER_SAVES_F6
222 #endif
223
224 #define CALLER_SAVES_D1
225 #define CALLER_SAVES_D2
226 #define CALLER_SAVES_D3
227 #define CALLER_SAVES_D4
228 #define CALLER_SAVES_D5
229 #if !defined(mingw32_HOST_OS)
230 #define CALLER_SAVES_D6
231 #endif
232
233 #define CALLER_SAVES_XMM1
234 #define CALLER_SAVES_XMM2
235 #define CALLER_SAVES_XMM3
236 #define CALLER_SAVES_XMM4
237 #define CALLER_SAVES_XMM5
238 #if !defined(mingw32_HOST_OS)
239 #define CALLER_SAVES_XMM6
240 #endif
241
242 #define CALLER_SAVES_YMM1
243 #define CALLER_SAVES_YMM2
244 #define CALLER_SAVES_YMM3
245 #define CALLER_SAVES_YMM4
246 #define CALLER_SAVES_YMM5
247 #if !defined(mingw32_HOST_OS)
248 #define CALLER_SAVES_YMM6
249 #endif
250
251 #define CALLER_SAVES_ZMM1
252 #define CALLER_SAVES_ZMM2
253 #define CALLER_SAVES_ZMM3
254 #define CALLER_SAVES_ZMM4
255 #define CALLER_SAVES_ZMM5
256 #if !defined(mingw32_HOST_OS)
257 #define CALLER_SAVES_ZMM6
258 #endif
259
260 #define MAX_REAL_VANILLA_REG 6
261 #define MAX_REAL_FLOAT_REG 6
262 #define MAX_REAL_DOUBLE_REG 6
263 #define MAX_REAL_LONG_REG 0
264 #define MAX_REAL_XMM_REG 6
265 #define MAX_REAL_YMM_REG 6
266 #define MAX_REAL_ZMM_REG 6
267
268 /* -----------------------------------------------------------------------------
269 The PowerPC register mapping
270
271 0 system glue? (caller-save, volatile)
272 1 SP (callee-save, non-volatile)
273 2 AIX, powerpc64-linux:
274 RTOC (a strange special case)
275 darwin:
276 (caller-save, volatile)
277 powerpc32-linux:
278 reserved for use by system
279
280 3-10 args/return (caller-save, volatile)
281 11,12 system glue? (caller-save, volatile)
282 13 on 64-bit: reserved for thread state pointer
283 on 32-bit: (callee-save, non-volatile)
284 14-31 (callee-save, non-volatile)
285
286 f0 (caller-save, volatile)
287 f1-f13 args/return (caller-save, volatile)
288 f14-f31 (callee-save, non-volatile)
289
290 \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes.
291 \tr{0}--\tr{12} are caller-save registers.
292
293 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
294
295 We can do the Whole Business with callee-save registers only!
296 -------------------------------------------------------------------------- */
297
298 #elif MACHREGS_powerpc
299
300 #define REG(x) __asm__(#x)
301
302 #define REG_R1 r14
303 #define REG_R2 r15
304 #define REG_R3 r16
305 #define REG_R4 r17
306 #define REG_R5 r18
307 #define REG_R6 r19
308 #define REG_R7 r20
309 #define REG_R8 r21
310
311 #if MACHREGS_darwin
312
313 #define REG_F1 f14
314 #define REG_F2 f15
315 #define REG_F3 f16
316 #define REG_F4 f17
317
318 #define REG_D1 f18
319 #define REG_D2 f19
320
321 #else
322
323 #define REG_F1 fr14
324 #define REG_F2 fr15
325 #define REG_F3 fr16
326 #define REG_F4 fr17
327
328 #define REG_D1 fr18
329 #define REG_D2 fr19
330
331 #endif
332
333 #define REG_Sp r22
334 #define REG_SpLim r24
335
336 #define REG_Hp r25
337
338 #define REG_Base r27
339
340 /* -----------------------------------------------------------------------------
341 The Sun SPARC register mapping
342
343 !! IMPORTANT: if you change this register mapping you must also update
344 compiler/nativeGen/SPARC/Regs.hs. That file handles the
345 mapping for the NCG. This one only affects via-c code.
346
347 The SPARC register (window) story: Remember, within the Haskell
348 Threaded World, we essentially ``shut down'' the register-window
349 mechanism---the window doesn't move at all while in this World. It
350 *does* move, of course, if we call out to arbitrary~C...
351
352 The %i, %l, and %o registers (8 each) are the input, local, and
353 output registers visible in one register window. The 8 %g (global)
354 registers are visible all the time.
355
356 zero: always zero
357 scratch: volatile across C-fn calls. used by linker.
358 app: usable by application
359 system: reserved for system
360
361 alloc: allocated to in the register allocator, intra-closure only
362
363 GHC usage v8 ABI v9 ABI
364 Global
365 %g0 zero zero zero
366 %g1 alloc scratch scrach
367 %g2 alloc app app
368 %g3 alloc app app
369 %g4 alloc app scratch
370 %g5 system scratch
371 %g6 system system
372 %g7 system system
373
374 Output: can be zapped by callee
375 %o0-o5 alloc caller saves
376 %o6 C stack ptr
377 %o7 C ret addr
378
379 Local: maintained by register windowing mechanism
380 %l0 alloc
381 %l1 R1
382 %l2 R2
383 %l3 R3
384 %l4 R4
385 %l5 R5
386 %l6 alloc
387 %l7 alloc
388
389 Input
390 %i0 Sp
391 %i1 Base
392 %i2 SpLim
393 %i3 Hp
394 %i4 alloc
395 %i5 R6
396 %i6 C frame ptr
397 %i7 C ret addr
398
399 The paired nature of the floating point registers causes complications for
400 the native code generator. For convenience, we pretend that the first 22
401 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
402 float (single) regs. The NCG acts accordingly. That means that the
403 following FP assignment is rather fragile, and should only be changed
404 with extreme care. The current scheme is:
405
406 %f0 /%f1 FP return from C
407 %f2 /%f3 D1
408 %f4 /%f5 D2
409 %f6 /%f7 ncg double spill tmp #1
410 %f8 /%f9 ncg double spill tmp #2
411 %f10/%f11 allocatable
412 %f12/%f13 allocatable
413 %f14/%f15 allocatable
414 %f16/%f17 allocatable
415 %f18/%f19 allocatable
416 %f20/%f21 allocatable
417
418 %f22 F1
419 %f23 F2
420 %f24 F3
421 %f25 F4
422 %f26 ncg single spill tmp #1
423 %f27 ncg single spill tmp #2
424 %f28 allocatable
425 %f29 allocatable
426 %f30 allocatable
427 %f31 allocatable
428
429 -------------------------------------------------------------------------- */
430
431 #elif MACHREGS_sparc
432
433 #define REG(x) __asm__("%" #x)
434
435 #define CALLER_SAVES_USER
436
437 #define CALLER_SAVES_F1
438 #define CALLER_SAVES_F2
439 #define CALLER_SAVES_F3
440 #define CALLER_SAVES_F4
441 #define CALLER_SAVES_D1
442 #define CALLER_SAVES_D2
443
444 #define REG_R1 l1
445 #define REG_R2 l2
446 #define REG_R3 l3
447 #define REG_R4 l4
448 #define REG_R5 l5
449 #define REG_R6 i5
450
451 #define REG_F1 f22
452 #define REG_F2 f23
453 #define REG_F3 f24
454 #define REG_F4 f25
455
456 /* for each of the double arg regs,
457 Dn_2 is the high half. */
458
459 #define REG_D1 f2
460 #define REG_D1_2 f3
461
462 #define REG_D2 f4
463 #define REG_D2_2 f5
464
465 #define REG_Sp i0
466 #define REG_SpLim i2
467
468 #define REG_Hp i3
469
470 #define REG_Base i1
471
472 #define NCG_FirstFloatReg f22
473
474 /* -----------------------------------------------------------------------------
475 The ARM EABI register mapping
476
477 Here we consider ARM mode (i.e. 32bit isns)
478 and also CPU with full VFPv3 implementation
479
480 ARM registers (see Chapter 5.1 in ARM IHI 0042D)
481
482 r15 PC The Program Counter.
483 r14 LR The Link Register.
484 r13 SP The Stack Pointer.
485 r12 IP The Intra-Procedure-call scratch register.
486 r11 v8 Variable-register 8.
487 r10 v7 Variable-register 7.
488 r9 v6/SB/TR Platform register. The meaning of this register is
489 defined by the platform standard.
490 r8 v5 Variable-register 5.
491 r7 v4 Variable register 4.
492 r6 v3 Variable register 3.
493 r5 v2 Variable register 2.
494 r4 v1 Variable register 1.
495 r3 a4 Argument / scratch register 4.
496 r2 a3 Argument / scratch register 3.
497 r1 a2 Argument / result / scratch register 2.
498 r0 a1 Argument / result / scratch register 1.
499
500 VFPv2/VFPv3/NEON registers
501 s0-s15/d0-d7/q0-q3 Argument / result/ scratch registers
502 s16-s31/d8-d15/q4-q7 callee-saved registers (must be preserved across
503 subrutine calls)
504
505 VFPv3/NEON registers (added to the VFPv2 registers set)
506 d16-d31/q8-q15 Argument / result/ scratch registers
507 ----------------------------------------------------------------------------- */
508
509 #elif MACHREGS_arm
510
511 #define REG(x) __asm__(#x)
512
513 #define REG_Base r4
514 #define REG_Sp r5
515 #define REG_Hp r6
516 #define REG_R1 r7
517 #define REG_R2 r8
518 #define REG_R3 r9
519 #define REG_R4 r10
520 #define REG_SpLim r11
521
522 #if !defined(arm_HOST_ARCH_PRE_ARMv6)
523 /* d8 */
524 #define REG_F1 s16
525 #define REG_F2 s17
526 /* d9 */
527 #define REG_F3 s18
528 #define REG_F4 s19
529
530 #define REG_D1 d10
531 #define REG_D2 d11
532 #endif
533
534 #else
535
536 #error Cannot find platform to give register info for
537
538 #endif
539
540 #else
541
542 #error Bad MACHREGS_NO_REGS value
543
544 #endif
545
546 /* -----------------------------------------------------------------------------
547 * These constants define how many stg registers will be used for
548 * passing arguments (and results, in the case of an unboxed-tuple
549 * return).
550 *
551 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
552 * highest STG register to occupy a real machine register, otherwise
553 * the calling conventions will needlessly shuffle data between the
554 * stack and memory-resident STG registers. We might occasionally
555 * set these macros to other values for testing, though.
556 *
557 * Registers above these values might still be used, for instance to
558 * communicate with PrimOps and RTS functions.
559 */
560
561 #ifndef MAX_REAL_VANILLA_REG
562 # if defined(REG_R10)
563 # define MAX_REAL_VANILLA_REG 10
564 # elif defined(REG_R9)
565 # define MAX_REAL_VANILLA_REG 9
566 # elif defined(REG_R8)
567 # define MAX_REAL_VANILLA_REG 8
568 # elif defined(REG_R7)
569 # define MAX_REAL_VANILLA_REG 7
570 # elif defined(REG_R6)
571 # define MAX_REAL_VANILLA_REG 6
572 # elif defined(REG_R5)
573 # define MAX_REAL_VANILLA_REG 5
574 # elif defined(REG_R4)
575 # define MAX_REAL_VANILLA_REG 4
576 # elif defined(REG_R3)
577 # define MAX_REAL_VANILLA_REG 3
578 # elif defined(REG_R2)
579 # define MAX_REAL_VANILLA_REG 2
580 # elif defined(REG_R1)
581 # define MAX_REAL_VANILLA_REG 1
582 # else
583 # define MAX_REAL_VANILLA_REG 0
584 # endif
585 #endif
586
587 #ifndef MAX_REAL_FLOAT_REG
588 # if defined(REG_F4)
589 # define MAX_REAL_FLOAT_REG 4
590 # elif defined(REG_F3)
591 # define MAX_REAL_FLOAT_REG 3
592 # elif defined(REG_F2)
593 # define MAX_REAL_FLOAT_REG 2
594 # elif defined(REG_F1)
595 # define MAX_REAL_FLOAT_REG 1
596 # else
597 # define MAX_REAL_FLOAT_REG 0
598 # endif
599 #endif
600
601 #ifndef MAX_REAL_DOUBLE_REG
602 # if defined(REG_D2)
603 # define MAX_REAL_DOUBLE_REG 2
604 # elif defined(REG_D1)
605 # define MAX_REAL_DOUBLE_REG 1
606 # else
607 # define MAX_REAL_DOUBLE_REG 0
608 # endif
609 #endif
610
611 #ifndef MAX_REAL_LONG_REG
612 # if defined(REG_L1)
613 # define MAX_REAL_LONG_REG 1
614 # else
615 # define MAX_REAL_LONG_REG 0
616 # endif
617 #endif
618
619 #ifndef MAX_REAL_XMM_REG
620 # if defined(REG_XMM6)
621 # define MAX_REAL_XMM_REG 6
622 # elif defined(REG_XMM5)
623 # define MAX_REAL_XMM_REG 5
624 # elif defined(REG_XMM4)
625 # define MAX_REAL_XMM_REG 4
626 # elif defined(REG_XMM3)
627 # define MAX_REAL_XMM_REG 3
628 # elif defined(REG_XMM2)
629 # define MAX_REAL_XMM_REG 2
630 # elif defined(REG_XMM1)
631 # define MAX_REAL_XMM_REG 1
632 # else
633 # define MAX_REAL_XMM_REG 0
634 # endif
635 #endif
636
637 /* define NO_ARG_REGS if we have no argument registers at all (we can
638 * optimise certain code paths using this predicate).
639 */
640 #if MAX_REAL_VANILLA_REG < 2
641 #define NO_ARG_REGS
642 #else
643 #undef NO_ARG_REGS
644 #endif
645
646 #endif /* MACHREGS_H */