add support for STG floating-point regs using VFPv3
[ghc.git] / includes / stg / MachRegs.h
1 /* -----------------------------------------------------------------------------
2 *
3 * (c) The GHC Team, 1998-2011
4 *
5 * Registers used in STG code. Might or might not correspond to
6 * actual machine registers.
7 *
8 * Do not #include this file directly: #include "Rts.h" instead.
9 *
10 * To understand the structure of the RTS headers, see the wiki:
11 * http://hackage.haskell.org/trac/ghc/wiki/Commentary/SourceTree/Includes
12 *
13 * ---------------------------------------------------------------------------*/
14
15 #ifndef MACHREGS_H
16 #define MACHREGS_H
17
18 /* This file is #included into Haskell code in the compiler: #defines
19 * only in here please.
20 */
21
22 /*
23 * Defining NO_REGS causes no global registers to be used. NO_REGS is
24 * typically defined by GHC, via a command-line option passed to gcc,
25 * when the -funregisterised flag is given.
26 *
27 * NB. When NO_REGS is on, calling & return conventions may be
28 * different. For example, all function arguments will be passed on
29 * the stack, and components of an unboxed tuple will be returned on
30 * the stack rather than in registers.
31 */
32 #ifndef NO_REGS
33
34 /* NOTE: when testing the platform in this file we must test either
35 * *_HOST_ARCH and *_TARGET_ARCH, depending on whether COMPILING_GHC
36 * is set. This is because when we're compiling the RTS and HC code,
37 * the platform we're running on is the HOST, but when compiling GHC
38 * we want to know about the register mapping on the TARGET platform.
39 */
40 #ifdef COMPILING_GHC
41 #define alpha_REGS alpha_TARGET_ARCH
42 #define hppa1_1_REGS hppa1_1_TARGET_ARCH
43 #define i386_REGS i386_TARGET_ARCH
44 #define x86_64_REGS x86_64_TARGET_ARCH
45 #define m68k_REGS m68k_TARGET_ARCH
46 #define mips_REGS (mipsel_TARGET_ARCH || mipseb_TARGET_ARCH)
47 #define powerpc_REGS (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH)
48 #define ia64_REGS ia64_TARGET_ARCH
49 #define sparc_REGS sparc_TARGET_ARCH
50 #define arm_REGS arm_TARGET_ARCH
51 #define darwin_REGS darwin_TARGET_OS
52 #else
53 #define alpha_REGS alpha_HOST_ARCH
54 #define hppa1_1_REGS hppa1_1_HOST_ARCH
55 #define i386_REGS i386_HOST_ARCH
56 #define x86_64_REGS x86_64_HOST_ARCH
57 #define m68k_REGS m68k_HOST_ARCH
58 #define mips_REGS (mipsel_HOST_ARCH || mipseb_HOST_ARCH)
59 #define powerpc_REGS (powerpc_HOST_ARCH || powerpc64_HOST_ARCH || rs6000_HOST_ARCH)
60 #define ia64_REGS ia64_HOST_ARCH
61 #define sparc_REGS sparc_HOST_ARCH
62 #define arm_REGS arm_HOST_ARCH
63 #define darwin_REGS darwin_HOST_OS
64 #endif
65
66 /* ----------------------------------------------------------------------------
67 Caller saves and callee-saves regs.
68
69 Caller-saves regs have to be saved around C-calls made from STG
70 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
71 is designated caller-saves in that machine's C calling convention.
72
73 As it stands, the only registers that are ever marked caller saves
74 are the RX, FX, DX and USER registers; as a result, if you
75 decide to caller save a system register (e.g. SP, HP, etc), note that
76 this code path is completely untested! -- EZY
77 -------------------------------------------------------------------------- */
78
79 /* -----------------------------------------------------------------------------
80 The DEC Alpha register mapping
81
82 Alpha registers
83 \tr{$9}--\tr{$14} are our ``prize'' callee-save registers.
84 \tr{$15} is the frame pointer, and \tr{$16}--\tr{$21} are argument
85 registers. (These are off-limits.) We can steal some of the \tr{$22}-and-up
86 caller-save registers provided we do the appropriate save/restore stuff.
87
88 \tr{$f2}--\tr{$f9} are some callee-save floating-point registers.
89
90 We cannot use \tr{$23} (aka t9), \tr{$24} (aka t10), \tr{$25} (aka
91 t11), \tr{$27} (aka pv), or \tr{$28} (aka at), because they are
92 occasionally required by the assembler to handle non-primitive
93 instructions (e.g. ldb, remq). Sigh!
94
95 Cheat sheet for GDB:
96
97 GDB here Main map
98 === ==== ========
99 s5 $14 R1
100 t1 $2 R2
101 t2 $3 R3
102 t3 $4 R4
103 t4 $5 R5
104 t5 $6 R6
105 t6 $7 R7
106 t7 $8 R8
107 s0 $9 Sp
108 s2 $11 SpLim
109 s3 $12 Hp
110 t8 $22 NCG_reserved
111 t12 $27 NCG_reserved
112 -------------------------------------------------------------------------- */
113
114 #if alpha_REGS
115 # define REG(x) __asm__("$" #x)
116
117 # define CALLER_SAVES_R2
118 # define CALLER_SAVES_R3
119 # define CALLER_SAVES_R4
120 # define CALLER_SAVES_R5
121 # define CALLER_SAVES_R6
122 # define CALLER_SAVES_R7
123 # define CALLER_SAVES_R8
124
125 # define CALLER_SAVES_USER
126
127 # define REG_R1 14
128 # define REG_R2 2
129 # define REG_R3 3
130 # define REG_R4 4
131 # define REG_R5 5
132 # define REG_R6 6
133 # define REG_R7 7
134 # define REG_R8 8
135
136 # define REG_F1 f2
137 # define REG_F2 f3
138 # define REG_F3 f4
139 # define REG_F4 f5
140
141 # define REG_D1 f6
142 # define REG_D2 f7
143
144 # define REG_Sp 9
145 # define REG_SpLim 11
146
147 # define REG_Hp 12
148
149 # define NCG_Reserved_I1 22
150 # define NCG_Reserved_I2 27
151 # define NCG_Reserved_F1 f29
152 # define NCG_Reserved_F2 f30
153
154 #endif /* alpha_REGS */
155
156 /* -----------------------------------------------------------------------------
157 The HP-PA register mapping
158
159 We cater for HP-PA 1.1.
160
161 \tr{%r0}--\tr{%r1} are special.
162 \tr{%r2} is the return pointer.
163 \tr{%r3} is the frame pointer.
164 \tr{%r4}--\tr{%r18} are callee-save registers.
165 \tr{%r19} is a linkage table register for HPUX 8.0 shared libraries.
166 \tr{%r20}--\tr{%r22} are caller-save registers.
167 \tr{%r23}--\tr{%r26} are parameter registers.
168 \tr{%r27} is a global data pointer.
169 \tr{%r28}--\tr{%r29} are temporaries.
170 \tr{%r30} is the stack pointer.
171 \tr{%r31} is a temporary.
172
173 \tr{%fr12}--\tr{%fr15} are some callee-save floating-point registers.
174 \tr{%fr8}--\tr{%fr11} are some available caller-save fl-pt registers.
175 -------------------------------------------------------------------------- */
176
177 #if hppa1_1_REGS
178
179 #define REG(x) __asm__("%" #x)
180
181 #define REG_R1 r11
182 #define REG_R2 r12
183 #define REG_R3 r13
184 #define REG_R4 r14
185 #define REG_R5 r15
186 #define REG_R6 r16
187 #define REG_R7 r17
188 #define REG_R8 r18
189
190 #define REG_F1 fr12
191 #define REG_F2 fr12R
192 #define REG_F3 fr13
193 #define REG_F4 fr13R
194
195 #define REG_D1 fr20 /* L & R */
196 #define REG_D2 fr21 /* L & R */
197
198 #define REG_Sp r4
199 #define REG_SpLim r6
200
201 #define REG_Hp r7
202
203 #define NCG_Reserved_I1 r28
204 #define NCG_Reserved_I2 r29
205 #define NCG_Reserved_F1 fr8
206 #define NCG_Reserved_F2 fr8R
207 #define NCG_Reserved_D1 fr10
208 #define NCG_Reserved_D2 fr11
209
210 #endif /* hppa */
211
212 /* -----------------------------------------------------------------------------
213 The x86 register mapping
214
215 Ok, we've only got 6 general purpose registers, a frame pointer and a
216 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
217 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
218 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
219
220 Reg STG-Reg
221 ---------------
222 ebx Base
223 ebp Sp
224 esi R1
225 edi Hp
226
227 Leaving SpLim out of the picture.
228 -------------------------------------------------------------------------- */
229
230
231 #if i386_REGS
232
233 #define REG(x) __asm__("%" #x)
234
235 #ifndef not_doing_dynamic_linking
236 #define REG_Base ebx
237 #endif
238 #define REG_Sp ebp
239
240 #ifndef STOLEN_X86_REGS
241 #define STOLEN_X86_REGS 4
242 #endif
243
244 #if STOLEN_X86_REGS >= 3
245 # define REG_R1 esi
246 #endif
247
248 #if STOLEN_X86_REGS >= 4
249 # define REG_Hp edi
250 #endif
251
252 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
253 #define MAX_REAL_FLOAT_REG 0
254 #define MAX_REAL_DOUBLE_REG 0
255 #define MAX_REAL_LONG_REG 0
256
257 #endif /* iX86 */
258
259 /* -----------------------------------------------------------------------------
260 The x86-64 register mapping
261
262 %rax caller-saves, don't steal this one
263 %rbx YES
264 %rcx arg reg, caller-saves
265 %rdx arg reg, caller-saves
266 %rsi arg reg, caller-saves
267 %rdi arg reg, caller-saves
268 %rbp YES (our *prime* register)
269 %rsp (unavailable - stack pointer)
270 %r8 arg reg, caller-saves
271 %r9 arg reg, caller-saves
272 %r10 caller-saves
273 %r11 caller-saves
274 %r12 YES
275 %r13 YES
276 %r14 YES
277 %r15 YES
278
279 %xmm0-7 arg regs, caller-saves
280 %xmm8-15 caller-saves
281
282 Use the caller-saves regs for Rn, because we don't always have to
283 save those (as opposed to Sp/Hp/SpLim etc. which always have to be
284 saved).
285
286 --------------------------------------------------------------------------- */
287
288 #if x86_64_REGS
289
290 #define REG(x) __asm__("%" #x)
291
292 #define REG_Base r13
293 #define REG_Sp rbp
294 #define REG_Hp r12
295 #define REG_R1 rbx
296 #define REG_R2 r14
297 #define REG_R3 rsi
298 #define REG_R4 rdi
299 #define REG_R5 r8
300 #define REG_R6 r9
301 #define REG_SpLim r15
302
303 #define REG_F1 xmm1
304 #define REG_F2 xmm2
305 #define REG_F3 xmm3
306 #define REG_F4 xmm4
307
308 #define REG_D1 xmm5
309 #define REG_D2 xmm6
310
311 #define CALLER_SAVES_R3
312 #define CALLER_SAVES_R4
313 #define CALLER_SAVES_R5
314 #define CALLER_SAVES_R6
315
316 #define CALLER_SAVES_F1
317 #define CALLER_SAVES_F2
318 #define CALLER_SAVES_F3
319 #define CALLER_SAVES_F4
320
321 #define CALLER_SAVES_D1
322 #define CALLER_SAVES_D2
323
324 #define MAX_REAL_VANILLA_REG 6
325 #define MAX_REAL_FLOAT_REG 4
326 #define MAX_REAL_DOUBLE_REG 2
327 #define MAX_REAL_LONG_REG 0
328
329 #endif /* x86_64 */
330
331 /* -----------------------------------------------------------------------------
332 The Motorola 680x0 register mapping
333
334 A Sun3 (mc680x0) has eight address registers, \tr{a0} to \tr{a7}, and
335 eight data registers, \tr{d0} to \tr{d7}. Address operations have to
336 be done through address registers; data registers are used for
337 comparison values and data.
338
339 Here's the register-usage picture for m68k boxes with GCC.
340
341 \begin{tabular}{ll}
342 a0 & used directly by GCC \\
343 a1 & used directly by GCC \\
344 \\
345 a2..a5 & callee-saved: available for STG registers \\
346 & (a5 may be special, ``global'' register for PIC?) \\
347 \\
348 a6 & C-stack frame pointer \\
349 a7 & C-stack pointer \\
350 \\
351 d0 & used directly by GCC \\
352 d1 & used directly by GCC \\
353 d2 & really needed for local optimisation by GCC \\
354 \\
355 d3..d7 & callee-saved: available for STG registers
356 \\
357 fp0 & call-clobbered \\
358 fp1 & call-clobbered \\
359 fp2..fp7 & callee-saved: available for STG registers
360 \end{tabular}
361 -------------------------------------------------------------------------- */
362
363 #if m68k_REGS
364
365 #define REG(x) __asm__(#x)
366
367 #define REG_Base a2
368
369 #define REG_Sp a3
370 #define REG_SpLim d3
371
372 #define REG_Hp d4
373
374 #define REG_R1 a5
375 #define REG_R2 d6
376 #define MAX_REAL_VANILLA_REG 2
377
378 #define REG_Ret d7
379
380 #define REG_F1 fp2
381 #define REG_F2 fp3
382 #define REG_F3 fp4
383 #define REG_F4 fp5
384
385 #define REG_D1 fp6
386 #define REG_D2 fp7
387
388 #endif /* m68k */
389
390 /* -----------------------------------------------------------------------------
391 The DECstation (MIPS) register mapping
392
393 Here's at least some simple stuff about registers on a MIPS.
394
395 \tr{s0}--\tr{s7} are callee-save integer registers; they are our
396 ``prize'' stolen registers. There is also a wad of callee-save
397 floating-point registers, \tr{$f20}--\tr{$f31}; we'll use some of
398 those.
399
400 \tr{t0}--\tr{t9} are caller-save (``temporary?'') integer registers.
401 We can steal some, but we might have to save/restore around ccalls.
402 -------------------------------------------------------------------------- */
403
404 #if mips_REGS
405
406 #define REG(x) __asm__("$" #x)
407
408 #define CALLER_SAVES_R5
409 #define CALLER_SAVES_R6
410 #define CALLER_SAVES_R7
411 #define CALLER_SAVES_R8
412
413 #define CALLER_SAVES_USER
414
415 #define REG_R1 16
416 #define REG_R2 17
417 #define REG_R3 18
418 #define REG_R4 19
419 #define REG_R5 12
420 #define REG_R6 13
421 #define REG_R7 14
422 #define REG_R8 15
423
424 #define REG_F1 f20
425 #define REG_F2 f22
426 #define REG_F3 f24
427 #define REG_F4 f26
428
429 #define REG_D1 f28
430 #define REG_D2 f30
431
432 #define REG_Sp 20
433 #define REG_SpLim 21
434
435 #define REG_Hp 22
436
437 #define REG_Base 30
438
439 #endif /* mipse[lb] */
440
441 /* -----------------------------------------------------------------------------
442 The PowerPC register mapping
443
444 0 system glue? (caller-save, volatile)
445 1 SP (callee-save, non-volatile)
446 2 AIX, powerpc64-linux:
447 RTOC (a strange special case)
448 darwin:
449 (caller-save, volatile)
450 powerpc32-linux:
451 reserved for use by system
452
453 3-10 args/return (caller-save, volatile)
454 11,12 system glue? (caller-save, volatile)
455 13 on 64-bit: reserved for thread state pointer
456 on 32-bit: (callee-save, non-volatile)
457 14-31 (callee-save, non-volatile)
458
459 f0 (caller-save, volatile)
460 f1-f13 args/return (caller-save, volatile)
461 f14-f31 (callee-save, non-volatile)
462
463 \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes.
464 \tr{0}--\tr{12} are caller-save registers.
465
466 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
467
468 We can do the Whole Business with callee-save registers only!
469 -------------------------------------------------------------------------- */
470
471 #if powerpc_REGS
472
473 #define REG(x) __asm__(#x)
474
475 #define REG_R1 r14
476 #define REG_R2 r15
477 #define REG_R3 r16
478 #define REG_R4 r17
479 #define REG_R5 r18
480 #define REG_R6 r19
481 #define REG_R7 r20
482 #define REG_R8 r21
483
484 #if darwin_REGS
485
486 #define REG_F1 f14
487 #define REG_F2 f15
488 #define REG_F3 f16
489 #define REG_F4 f17
490
491 #define REG_D1 f18
492 #define REG_D2 f19
493
494 #else
495
496 #define REG_F1 fr14
497 #define REG_F2 fr15
498 #define REG_F3 fr16
499 #define REG_F4 fr17
500
501 #define REG_D1 fr18
502 #define REG_D2 fr19
503
504 #endif
505
506 #define REG_Sp r22
507 #define REG_SpLim r24
508
509 #define REG_Hp r25
510
511 #define REG_Base r27
512
513 #endif /* powerpc */
514
515 /* -----------------------------------------------------------------------------
516 The IA64 register mapping
517
518 We place the general registers in the locals area of the register stack,
519 so that the call mechanism takes care of saving them for us. We reserve
520 the first 16 for gcc's use - since gcc uses the highest used register to
521 determine the register stack frame size, this gives us a constant size
522 register stack frame.
523
524 \tr{f16-f32} are the callee-saved floating point registers.
525 -------------------------------------------------------------------------- */
526
527 #if ia64_REGS
528
529 #define REG(x) __asm__(#x)
530
531 #define REG_R1 loc16
532 #define REG_R2 loc17
533 #define REG_R3 loc18
534 #define REG_R4 loc19
535 #define REG_R5 loc20
536 #define REG_R6 loc21
537 #define REG_R7 loc22
538 #define REG_R8 loc23
539
540 #define REG_F1 f16
541 #define REG_F2 f17
542 #define REG_F3 f18
543 #define REG_F4 f19
544
545 #define REG_D1 f20
546 #define REG_D2 f21
547
548 #define REG_Sp loc24
549 #define REG_SpLim loc26
550
551 #define REG_Hp loc27
552
553 #endif /* ia64 */
554
555 /* -----------------------------------------------------------------------------
556 The Sun SPARC register mapping
557
558 !! IMPORTANT: if you change this register mapping you must also update
559 compiler/nativeGen/SPARC/Regs.hs. That file handles the
560 mapping for the NCG. This one only affects via-c code.
561
562 The SPARC register (window) story: Remember, within the Haskell
563 Threaded World, we essentially ``shut down'' the register-window
564 mechanism---the window doesn't move at all while in this World. It
565 *does* move, of course, if we call out to arbitrary~C...
566
567 The %i, %l, and %o registers (8 each) are the input, local, and
568 output registers visible in one register window. The 8 %g (global)
569 registers are visible all the time.
570
571 zero: always zero
572 scratch: volatile across C-fn calls. used by linker.
573 app: usable by application
574 system: reserved for system
575
576 alloc: allocated to in the register allocator, intra-closure only
577
578 GHC usage v8 ABI v9 ABI
579 Global
580 %g0 zero zero zero
581 %g1 alloc scratch scrach
582 %g2 alloc app app
583 %g3 alloc app app
584 %g4 alloc app scratch
585 %g5 system scratch
586 %g6 system system
587 %g7 system system
588
589 Output: can be zapped by callee
590 %o0-o5 alloc caller saves
591 %o6 C stack ptr
592 %o7 C ret addr
593
594 Local: maintained by register windowing mechanism
595 %l0 alloc
596 %l1 R1
597 %l2 R2
598 %l3 R3
599 %l4 R4
600 %l5 R5
601 %l6 alloc
602 %l7 alloc
603
604 Input
605 %i0 Sp
606 %i1 Base
607 %i2 SpLim
608 %i3 Hp
609 %i4 alloc
610 %i5 R6
611 %i6 C frame ptr
612 %i7 C ret addr
613
614 The paired nature of the floating point registers causes complications for
615 the native code generator. For convenience, we pretend that the first 22
616 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
617 float (single) regs. The NCG acts accordingly. That means that the
618 following FP assignment is rather fragile, and should only be changed
619 with extreme care. The current scheme is:
620
621 %f0 /%f1 FP return from C
622 %f2 /%f3 D1
623 %f4 /%f5 D2
624 %f6 /%f7 ncg double spill tmp #1
625 %f8 /%f9 ncg double spill tmp #2
626 %f10/%f11 allocatable
627 %f12/%f13 allocatable
628 %f14/%f15 allocatable
629 %f16/%f17 allocatable
630 %f18/%f19 allocatable
631 %f20/%f21 allocatable
632
633 %f22 F1
634 %f23 F2
635 %f24 F3
636 %f25 F4
637 %f26 ncg single spill tmp #1
638 %f27 ncg single spill tmp #2
639 %f28 allocatable
640 %f29 allocatable
641 %f30 allocatable
642 %f31 allocatable
643
644 -------------------------------------------------------------------------- */
645
646 #if sparc_REGS
647
648 #define REG(x) __asm__("%" #x)
649
650 #define CALLER_SAVES_USER
651
652 #define CALLER_SAVES_F1
653 #define CALLER_SAVES_F2
654 #define CALLER_SAVES_F3
655 #define CALLER_SAVES_F4
656 #define CALLER_SAVES_D1
657 #define CALLER_SAVES_D2
658
659 #define REG_R1 l1
660 #define REG_R2 l2
661 #define REG_R3 l3
662 #define REG_R4 l4
663 #define REG_R5 l5
664 #define REG_R6 i5
665
666 #define REG_F1 f22
667 #define REG_F2 f23
668 #define REG_F3 f24
669 #define REG_F4 f25
670
671 /* for each of the double arg regs,
672 Dn_2 is the high half. */
673
674 #define REG_D1 f2
675 #define REG_D1_2 f3
676
677 #define REG_D2 f4
678 #define REG_D2_2 f5
679
680 #define REG_Sp i0
681 #define REG_SpLim i2
682
683 #define REG_Hp i3
684
685 #define REG_Base i1
686
687 /*
688 #define NCG_SpillTmp_I1 g1
689 #define NCG_SpillTmp_I2 g2
690 #define NCG_SpillTmp_F1 f26
691 #define NCG_SpillTmp_F2 f27
692 #define NCG_SpillTmp_D1 f6
693 #define NCG_SpillTmp_D2 f8
694 */
695
696 #define NCG_FirstFloatReg f22
697
698 #endif /* sparc */
699
700 /* -----------------------------------------------------------------------------
701 The ARM EABI register mapping
702
703 Here we consider ARM mode (i.e. 32bit isns)
704 and also CPU with full VFPv3 implementation
705
706 ARM registers (see Chapter 5.1 in ARM IHI 0042D)
707
708 r15 PC The Program Counter.
709 r14 LR The Link Register.
710 r13 SP The Stack Pointer.
711 r12 IP The Intra-Procedure-call scratch register.
712 r11 v8 Variable-register 8.
713 r10 v7 Variable-register 7.
714 r9 v6/SB/TR Platform register. The meaning of this register is
715 defined by the platform standard.
716 r8 v5 Variable-register 5.
717 r7 v4 Variable register 4.
718 r6 v3 Variable register 3.
719 r5 v2 Variable register 2.
720 r4 v1 Variable register 1.
721 r3 a4 Argument / scratch register 4.
722 r2 a3 Argument / scratch register 3.
723 r1 a2 Argument / result / scratch register 2.
724 r0 a1 Argument / result / scratch register 1.
725
726 VFPv2/VFPv3/NEON registers
727 s0-s15/d0-d7/q0-q3 Argument / result/ scratch registers
728 s16-s31/d8-d15/q4-q7 callee-saved registers (must be preserved across
729 subrutine calls)
730
731 VFPv3/NEON registers (added to the VFPv2 registers set)
732 d16-d31/q8-q15 Argument / result/ scratch registers
733 ----------------------------------------------------------------------------- */
734
735
736 #if arm_REGS
737
738 #define REG(x) __asm__(#x)
739
740 #define REG_Base r4
741 #define REG_Sp r5
742 #define REG_Hp r6
743 #define REG_R1 r7
744 #define REG_R2 r8
745 #define REG_R3 r9
746 #define REG_R4 r10
747 #define REG_SpLim r11
748
749 /* d8 */
750 #define REG_F1 s16
751 #define REG_F2 s17
752 /* d9 */
753 #define REG_F3 s18
754 #define REG_F4 s19
755
756 #define REG_D1 d10
757 #define REG_D2 d11
758
759 #endif /* arm */
760
761 #endif /* NO_REGS */
762
763 /* -----------------------------------------------------------------------------
764 * These constants define how many stg registers will be used for
765 * passing arguments (and results, in the case of an unboxed-tuple
766 * return).
767 *
768 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
769 * highest STG register to occupy a real machine register, otherwise
770 * the calling conventions will needlessly shuffle data between the
771 * stack and memory-resident STG registers. We might occasionally
772 * set these macros to other values for testing, though.
773 *
774 * Registers above these values might still be used, for instance to
775 * communicate with PrimOps and RTS functions.
776 */
777
778 #ifndef MAX_REAL_VANILLA_REG
779 # if defined(REG_R8)
780 # define MAX_REAL_VANILLA_REG 8
781 # elif defined(REG_R7)
782 # define MAX_REAL_VANILLA_REG 7
783 # elif defined(REG_R6)
784 # define MAX_REAL_VANILLA_REG 6
785 # elif defined(REG_R5)
786 # define MAX_REAL_VANILLA_REG 5
787 # elif defined(REG_R4)
788 # define MAX_REAL_VANILLA_REG 4
789 # elif defined(REG_R3)
790 # define MAX_REAL_VANILLA_REG 3
791 # elif defined(REG_R2)
792 # define MAX_REAL_VANILLA_REG 2
793 # elif defined(REG_R1)
794 # define MAX_REAL_VANILLA_REG 1
795 # else
796 # define MAX_REAL_VANILLA_REG 0
797 # endif
798 #endif
799
800 #ifndef MAX_REAL_FLOAT_REG
801 # if defined(REG_F4)
802 # define MAX_REAL_FLOAT_REG 4
803 # elif defined(REG_F3)
804 # define MAX_REAL_FLOAT_REG 3
805 # elif defined(REG_F2)
806 # define MAX_REAL_FLOAT_REG 2
807 # elif defined(REG_F1)
808 # define MAX_REAL_FLOAT_REG 1
809 # else
810 # define MAX_REAL_FLOAT_REG 0
811 # endif
812 #endif
813
814 #ifndef MAX_REAL_DOUBLE_REG
815 # if defined(REG_D2)
816 # define MAX_REAL_DOUBLE_REG 2
817 # elif defined(REG_D1)
818 # define MAX_REAL_DOUBLE_REG 1
819 # else
820 # define MAX_REAL_DOUBLE_REG 0
821 # endif
822 #endif
823
824 #ifndef MAX_REAL_LONG_REG
825 # if defined(REG_L1)
826 # define MAX_REAL_LONG_REG 1
827 # else
828 # define MAX_REAL_LONG_REG 0
829 # endif
830 #endif
831
832 /* define NO_ARG_REGS if we have no argument registers at all (we can
833 * optimise certain code paths using this predicate).
834 */
835 #if MAX_REAL_VANILLA_REG < 2
836 #define NO_ARG_REGS
837 #else
838 #undef NO_ARG_REGS
839 #endif
840
841 #endif /* MACHREGS_H */