includes/stg/MachRegs.h

   1 /* -----------------------------------------------------------------------------
   2  *
   3  * (c) The GHC Team, 1998-2011
   4  *
   5  * Registers used in STG code.  Might or might not correspond to
   6  * actual machine registers.
   7  *
   8  * Do not #include this file directly: #include "Rts.h" instead.
   9  *
  10  * To understand the structure of the RTS headers, see the wiki:
  11  *   http://hackage.haskell.org/trac/ghc/wiki/Commentary/SourceTree/Includes
  12  *
  13  * ---------------------------------------------------------------------------*/
  14
  15 #ifndef MACHREGS_H
  16 #define MACHREGS_H
  17
  18 /* This file is #included into Haskell code in the compiler: #defines
  19  * only in here please.
  20  */
  21
  22 /*
  23  * Defining NO_REGS causes no global registers to be used.  NO_REGS is
  24  * typically defined by GHC, via a command-line option passed to gcc,
  25  * when the -funregisterised flag is given.
  26  *
  27  * NB. When NO_REGS is on, calling & return conventions may be
  28  * different.  For example, all function arguments will be passed on
  29  * the stack, and components of an unboxed tuple will be returned on
  30  * the stack rather than in registers.
  31  */
  32 #ifndef NO_REGS
  33
  34 /* NOTE: when testing the platform in this file we must test either
  35  * *_HOST_ARCH and *_TARGET_ARCH, depending on whether COMPILING_GHC
  36  * is set.  This is because when we're compiling the RTS and HC code,
  37  * the platform we're running on is the HOST, but when compiling GHC
  38  * we want to know about the register mapping on the TARGET platform.
  39  */
  40 #ifdef COMPILING_GHC
  41 #define i386_REGS     i386_TARGET_ARCH
  42 #define x86_64_REGS   x86_64_TARGET_ARCH
  43 #define powerpc_REGS  (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH)
  44 #define sparc_REGS    sparc_TARGET_ARCH
  45 #define arm_REGS      arm_TARGET_ARCH
  46 #define darwin_REGS   darwin_TARGET_OS
  47 #else
  48 #define i386_REGS     i386_HOST_ARCH
  49 #define x86_64_REGS   x86_64_HOST_ARCH
  50 #define powerpc_REGS  (powerpc_HOST_ARCH || powerpc64_HOST_ARCH || rs6000_HOST_ARCH)
  51 #define sparc_REGS    sparc_HOST_ARCH
  52 #define arm_REGS      arm_HOST_ARCH
  53 #define darwin_REGS   darwin_HOST_OS
  54 #endif
  55
  56 /* ----------------------------------------------------------------------------
  57    Caller saves and callee-saves regs.
  58
  59    Caller-saves regs have to be saved around C-calls made from STG
  60    land, so this file defines CALLER_SAVES_<reg> for each <reg> that
  61    is designated caller-saves in that machine's C calling convention.
  62
  63    As it stands, the only registers that are ever marked caller saves
  64    are the RX, FX, DX and USER registers; as a result, if you
  65    decide to caller save a system register (e.g. SP, HP, etc), note that
  66    this code path is completely untested! -- EZY
  67    -------------------------------------------------------------------------- */
  68
  69 /* -----------------------------------------------------------------------------
  70    The x86 register mapping
  71
  72    Ok, we've only got 6 general purpose registers, a frame pointer and a
  73    stack pointer.  \tr{%eax} and \tr{%edx} are return values from C functions,
  74    hence they get trashed across ccalls and are caller saves. \tr{%ebx},
  75    \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
  76
  77    Reg     STG-Reg
  78    ---------------
  79    ebx     Base
  80    ebp     Sp
  81    esi     R1
  82    edi     Hp
  83
  84    Leaving SpLim out of the picture.
  85    -------------------------------------------------------------------------- */
  86
  87 #if i386_REGS
  88
  89 #define REG(x) __asm__("%" #x)
  90
  91 #ifndef not_doing_dynamic_linking
  92 #define REG_Base    ebx
  93 #endif
  94 #define REG_Sp      ebp
  95
  96 #ifndef STOLEN_X86_REGS
  97 #define STOLEN_X86_REGS 4
  98 #endif
  99
 100 #if STOLEN_X86_REGS >= 3
 101 # define REG_R1     esi
 102 #endif
 103
 104 #if STOLEN_X86_REGS >= 4
 105 # define REG_Hp     edi
 106 #endif
 107
 108 #define MAX_REAL_VANILLA_REG 1  /* always, since it defines the entry conv */
 109 #define MAX_REAL_FLOAT_REG   0
 110 #define MAX_REAL_DOUBLE_REG  0
 111 #define MAX_REAL_LONG_REG    0
 112
 113 #endif /* iX86 */
 114
 115 /* -----------------------------------------------------------------------------
 116   The x86-64 register mapping
 117
 118   %rax          caller-saves, don't steal this one
 119   %rbx          YES
 120   %rcx          arg reg, caller-saves
 121   %rdx          arg reg, caller-saves
 122   %rsi          arg reg, caller-saves
 123   %rdi          arg reg, caller-saves
 124   %rbp          YES (our *prime* register)
 125   %rsp          (unavailable - stack pointer)
 126   %r8           arg reg, caller-saves
 127   %r9           arg reg, caller-saves
 128   %r10          caller-saves
 129   %r11          caller-saves
 130   %r12          YES
 131   %r13          YES
 132   %r14          YES
 133   %r15          YES
 134
 135   %xmm0-7       arg regs, caller-saves
 136   %xmm8-15      caller-saves
 137
 138   Use the caller-saves regs for Rn, because we don't always have to
 139   save those (as opposed to Sp/Hp/SpLim etc. which always have to be
 140   saved).
 141
 142   --------------------------------------------------------------------------- */
 143
 144 #if x86_64_REGS
 145
 146 #define REG(x) __asm__("%" #x)
 147
 148 #define REG_Base  r13
 149 #define REG_Sp    rbp
 150 #define REG_Hp    r12
 151 #define REG_R1    rbx
 152 #define REG_R2    r14
 153 #define REG_R3    rsi
 154 #define REG_R4    rdi
 155 #define REG_R5    r8
 156 #define REG_R6    r9
 157 #define REG_SpLim r15
 158
 159 #define REG_F1    xmm1
 160 #define REG_F2    xmm2
 161 #define REG_F3    xmm3
 162 #define REG_F4    xmm4
 163
 164 #define REG_D1    xmm5
 165 #define REG_D2    xmm6
 166
 167 #define CALLER_SAVES_R3
 168 #define CALLER_SAVES_R4
 169 #define CALLER_SAVES_R5
 170 #define CALLER_SAVES_R6
 171
 172 #define CALLER_SAVES_F1
 173 #define CALLER_SAVES_F2
 174 #define CALLER_SAVES_F3
 175 #define CALLER_SAVES_F4
 176
 177 #define CALLER_SAVES_D1
 178 #define CALLER_SAVES_D2
 179
 180 #define MAX_REAL_VANILLA_REG 6
 181 #define MAX_REAL_FLOAT_REG   4
 182 #define MAX_REAL_DOUBLE_REG  2
 183 #define MAX_REAL_LONG_REG    0
 184
 185 #endif /* x86_64 */
 186
 187 /* -----------------------------------------------------------------------------
 188    The PowerPC register mapping
 189
 190    0            system glue?    (caller-save, volatile)
 191    1            SP              (callee-save, non-volatile)
 192    2            AIX, powerpc64-linux:
 193                     RTOC        (a strange special case)
 194                 darwin:
 195                                 (caller-save, volatile)
 196                 powerpc32-linux:
 197                                 reserved for use by system
 198
 199    3-10         args/return     (caller-save, volatile)
 200    11,12        system glue?    (caller-save, volatile)
 201    13           on 64-bit:      reserved for thread state pointer
 202                 on 32-bit:      (callee-save, non-volatile)
 203    14-31                        (callee-save, non-volatile)
 204
 205    f0                           (caller-save, volatile)
 206    f1-f13       args/return     (caller-save, volatile)
 207    f14-f31                      (callee-save, non-volatile)
 208
 209    \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes.
 210    \tr{0}--\tr{12} are caller-save registers.
 211
 212    \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
 213
 214    We can do the Whole Business with callee-save registers only!
 215    -------------------------------------------------------------------------- */
 216
 217 #if powerpc_REGS
 218
 219 #define REG(x) __asm__(#x)
 220
 221 #define REG_R1          r14
 222 #define REG_R2          r15
 223 #define REG_R3          r16
 224 #define REG_R4          r17
 225 #define REG_R5          r18
 226 #define REG_R6          r19
 227 #define REG_R7          r20
 228 #define REG_R8          r21
 229
 230 #if darwin_REGS
 231
 232 #define REG_F1          f14
 233 #define REG_F2          f15
 234 #define REG_F3          f16
 235 #define REG_F4          f17
 236
 237 #define REG_D1          f18
 238 #define REG_D2          f19
 239
 240 #else
 241
 242 #define REG_F1          fr14
 243 #define REG_F2          fr15
 244 #define REG_F3          fr16
 245 #define REG_F4          fr17
 246
 247 #define REG_D1          fr18
 248 #define REG_D2          fr19
 249
 250 #endif
 251
 252 #define REG_Sp          r22
 253 #define REG_SpLim       r24
 254
 255 #define REG_Hp          r25
 256
 257 #define REG_Base        r27
 258
 259 #endif /* powerpc */
 260
 261 /* -----------------------------------------------------------------------------
 262    The Sun SPARC register mapping
 263
 264    !! IMPORTANT: if you change this register mapping you must also update
 265                  compiler/nativeGen/SPARC/Regs.hs. That file handles the
 266                  mapping for the NCG. This one only affects via-c code.
 267
 268    The SPARC register (window) story: Remember, within the Haskell
 269    Threaded World, we essentially ``shut down'' the register-window
 270    mechanism---the window doesn't move at all while in this World.  It
 271    *does* move, of course, if we call out to arbitrary~C...
 272
 273    The %i, %l, and %o registers (8 each) are the input, local, and
 274    output registers visible in one register window.  The 8 %g (global)
 275    registers are visible all the time.
 276
 277       zero: always zero
 278    scratch: volatile across C-fn calls. used by linker.
 279        app: usable by application
 280     system: reserved for system
 281
 282      alloc: allocated to in the register allocator, intra-closure only
 283
 284                 GHC usage     v8 ABI        v9 ABI
 285    Global
 286      %g0        zero        zero          zero
 287      %g1        alloc       scratch       scrach
 288      %g2        alloc       app           app
 289      %g3        alloc       app           app
 290      %g4        alloc       app           scratch
 291      %g5                    system        scratch
 292      %g6                    system        system
 293      %g7                    system        system
 294
 295    Output: can be zapped by callee
 296      %o0-o5     alloc       caller saves
 297      %o6                    C stack ptr
 298      %o7                    C ret addr
 299
 300    Local: maintained by register windowing mechanism
 301      %l0        alloc
 302      %l1        R1
 303      %l2        R2
 304      %l3        R3
 305      %l4        R4
 306      %l5        R5
 307      %l6        alloc
 308      %l7        alloc
 309
 310    Input
 311      %i0        Sp
 312      %i1        Base
 313      %i2        SpLim
 314      %i3        Hp
 315      %i4        alloc
 316      %i5        R6
 317      %i6                    C frame ptr
 318      %i7                    C ret addr
 319
 320    The paired nature of the floating point registers causes complications for
 321    the native code generator.  For convenience, we pretend that the first 22
 322    fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
 323    float (single) regs.  The NCG acts accordingly.  That means that the
 324    following FP assignment is rather fragile, and should only be changed
 325    with extreme care.  The current scheme is:
 326
 327       %f0 /%f1    FP return from C
 328       %f2 /%f3    D1
 329       %f4 /%f5    D2
 330       %f6 /%f7    ncg double spill tmp #1
 331       %f8 /%f9    ncg double spill tmp #2
 332       %f10/%f11   allocatable
 333       %f12/%f13   allocatable
 334       %f14/%f15   allocatable
 335       %f16/%f17   allocatable
 336       %f18/%f19   allocatable
 337       %f20/%f21   allocatable
 338
 339       %f22        F1
 340       %f23        F2
 341       %f24        F3
 342       %f25        F4
 343       %f26        ncg single spill tmp #1
 344       %f27        ncg single spill tmp #2
 345       %f28        allocatable
 346       %f29        allocatable
 347       %f30        allocatable
 348       %f31        allocatable
 349
 350    -------------------------------------------------------------------------- */
 351
 352 #if sparc_REGS
 353
 354 #define REG(x) __asm__("%" #x)
 355
 356 #define CALLER_SAVES_USER
 357
 358 #define CALLER_SAVES_F1
 359 #define CALLER_SAVES_F2
 360 #define CALLER_SAVES_F3
 361 #define CALLER_SAVES_F4
 362 #define CALLER_SAVES_D1
 363 #define CALLER_SAVES_D2
 364
 365 #define REG_R1          l1
 366 #define REG_R2          l2
 367 #define REG_R3          l3
 368 #define REG_R4          l4
 369 #define REG_R5          l5
 370 #define REG_R6          i5
 371
 372 #define REG_F1          f22
 373 #define REG_F2          f23
 374 #define REG_F3          f24
 375 #define REG_F4          f25
 376
 377 /* for each of the double arg regs,
 378    Dn_2 is the high half. */
 379
 380 #define REG_D1          f2
 381 #define REG_D1_2        f3
 382
 383 #define REG_D2          f4
 384 #define REG_D2_2        f5
 385
 386 #define REG_Sp          i0
 387 #define REG_SpLim       i2
 388
 389 #define REG_Hp          i3
 390
 391 #define REG_Base        i1
 392
 393 /*
 394 #define NCG_SpillTmp_I1 g1
 395 #define NCG_SpillTmp_I2 g2
 396 #define NCG_SpillTmp_F1 f26
 397 #define NCG_SpillTmp_F2 f27
 398 #define NCG_SpillTmp_D1 f6
 399 #define NCG_SpillTmp_D2 f8
 400 */
 401
 402 #define NCG_FirstFloatReg f22
 403
 404 #endif /* sparc */
 405
 406 /* -----------------------------------------------------------------------------
 407    The ARM EABI register mapping
 408
 409    Here we consider ARM mode (i.e. 32bit isns)
 410    and also CPU with full VFPv3 implementation
 411
 412    ARM registers (see Chapter 5.1 in ARM IHI 0042D)
 413
 414    r15  PC         The Program Counter.
 415    r14  LR         The Link Register.
 416    r13  SP         The Stack Pointer.
 417    r12  IP         The Intra-Procedure-call scratch register.
 418    r11  v8         Variable-register 8.
 419    r10  v7         Variable-register 7.
 420    r9   v6/SB/TR   Platform register. The meaning of this register is
 421                    defined by the platform standard.
 422    r8   v5         Variable-register 5.
 423    r7   v4         Variable register 4.
 424    r6   v3         Variable register 3.
 425    r5   v2         Variable register 2.
 426    r4   v1         Variable register 1.
 427    r3   a4         Argument / scratch register 4.
 428    r2   a3         Argument / scratch register 3.
 429    r1   a2         Argument / result / scratch register 2.
 430    r0   a1         Argument / result / scratch register 1.
 431
 432    VFPv2/VFPv3/NEON registers
 433    s0-s15/d0-d7/q0-q3    Argument / result/ scratch registers
 434    s16-s31/d8-d15/q4-q7  callee-saved registers (must be preserved across
 435                          subrutine calls)
 436
 437    VFPv3/NEON registers (added to the VFPv2 registers set)
 438    d16-d31/q8-q15        Argument / result/ scratch registers
 439    ----------------------------------------------------------------------------- */
 440
 441
 442 #if arm_REGS
 443
 444 #define REG(x) __asm__(#x)
 445
 446 #define REG_Base        r4
 447 #define REG_Sp          r5
 448 #define REG_Hp          r6
 449 #define REG_R1          r7
 450 #define REG_R2          r8
 451 #define REG_R3          r9
 452 #define REG_R4          r10
 453 #define REG_SpLim       r11
 454
 455 #if !defined(arm_HOST_ARCH_PRE_ARMv6)
 456 /* d8 */
 457 #define REG_F1    s16
 458 #define REG_F2    s17
 459 /* d9 */
 460 #define REG_F3    s18
 461 #define REG_F4    s19
 462
 463 #define REG_D1    d10
 464 #define REG_D2    d11
 465 #endif
 466
 467 #endif /* arm */
 468
 469 #endif /* NO_REGS */
 470
 471 /* -----------------------------------------------------------------------------
 472  * These constants define how many stg registers will be used for
 473  * passing arguments (and results, in the case of an unboxed-tuple
 474  * return).
 475  *
 476  * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
 477  * highest STG register to occupy a real machine register, otherwise
 478  * the calling conventions will needlessly shuffle data between the
 479  * stack and memory-resident STG registers.  We might occasionally
 480  * set these macros to other values for testing, though.
 481  *
 482  * Registers above these values might still be used, for instance to
 483  * communicate with PrimOps and RTS functions.
 484  */
 485
 486 #ifndef MAX_REAL_VANILLA_REG
 487 #  if   defined(REG_R10)
 488 #  define MAX_REAL_VANILLA_REG 10
 489 #  elif   defined(REG_R9)
 490 #  define MAX_REAL_VANILLA_REG 9
 491 #  elif   defined(REG_R8)
 492 #  define MAX_REAL_VANILLA_REG 8
 493 #  elif defined(REG_R7)
 494 #  define MAX_REAL_VANILLA_REG 7
 495 #  elif defined(REG_R6)
 496 #  define MAX_REAL_VANILLA_REG 6
 497 #  elif defined(REG_R5)
 498 #  define MAX_REAL_VANILLA_REG 5
 499 #  elif defined(REG_R4)
 500 #  define MAX_REAL_VANILLA_REG 4
 501 #  elif defined(REG_R3)
 502 #  define MAX_REAL_VANILLA_REG 3
 503 #  elif defined(REG_R2)
 504 #  define MAX_REAL_VANILLA_REG 2
 505 #  elif defined(REG_R1)
 506 #  define MAX_REAL_VANILLA_REG 1
 507 #  else
 508 #  define MAX_REAL_VANILLA_REG 0
 509 #  endif
 510 #endif
 511
 512 #ifndef MAX_REAL_FLOAT_REG
 513 #  if   defined(REG_F4)
 514 #  define MAX_REAL_FLOAT_REG 4
 515 #  elif defined(REG_F3)
 516 #  define MAX_REAL_FLOAT_REG 3
 517 #  elif defined(REG_F2)
 518 #  define MAX_REAL_FLOAT_REG 2
 519 #  elif defined(REG_F1)
 520 #  define MAX_REAL_FLOAT_REG 1
 521 #  else
 522 #  define MAX_REAL_FLOAT_REG 0
 523 #  endif
 524 #endif
 525
 526 #ifndef MAX_REAL_DOUBLE_REG
 527 #  if   defined(REG_D2)
 528 #  define MAX_REAL_DOUBLE_REG 2
 529 #  elif defined(REG_D1)
 530 #  define MAX_REAL_DOUBLE_REG 1
 531 #  else
 532 #  define MAX_REAL_DOUBLE_REG 0
 533 #  endif
 534 #endif
 535
 536 #ifndef MAX_REAL_LONG_REG
 537 #  if   defined(REG_L1)
 538 #  define MAX_REAL_LONG_REG 1
 539 #  else
 540 #  define MAX_REAL_LONG_REG 0
 541 #  endif
 542 #endif
 543
 544 /* define NO_ARG_REGS if we have no argument registers at all (we can
 545  * optimise certain code paths using this predicate).
 546  */
 547 #if MAX_REAL_VANILLA_REG < 2
 548 #define NO_ARG_REGS
 549 #else
 550 #undef NO_ARG_REGS
 551 #endif
 552
 553 #endif /* MACHREGS_H */