cmm: Expose machine's stack and return address register
[ghc.git] / includes / stg / MachRegs.h
1 /* -----------------------------------------------------------------------------
2 *
3 * (c) The GHC Team, 1998-2014
4 *
5 * Registers used in STG code. Might or might not correspond to
6 * actual machine registers.
7 *
8 * Do not #include this file directly: #include "Rts.h" instead.
9 *
10 * To understand the structure of the RTS headers, see the wiki:
11 * http://ghc.haskell.org/trac/ghc/wiki/Commentary/SourceTree/Includes
12 *
13 * ---------------------------------------------------------------------------*/
14
15 #ifndef MACHREGS_H
16 #define MACHREGS_H
17
18 /* This file is #included into Haskell code in the compiler: #defines
19 * only in here please.
20 */
21
22 /*
23 * Undefine these as a precaution: some of them were found to be
24 * defined by system headers on ARM/Linux.
25 */
26 #undef REG_R1
27 #undef REG_R2
28 #undef REG_R3
29 #undef REG_R4
30 #undef REG_R5
31 #undef REG_R6
32 #undef REG_R7
33 #undef REG_R8
34 #undef REG_R9
35 #undef REG_R10
36
37 /*
38 * Defining MACHREGS_NO_REGS to 1 causes no global registers to be used.
39 * MACHREGS_NO_REGS is typically controlled by NO_REGS, which is
40 * typically defined by GHC, via a command-line option passed to gcc,
41 * when the -funregisterised flag is given.
42 *
43 * NB. When MACHREGS_NO_REGS to 1, calling & return conventions may be
44 * different. For example, all function arguments will be passed on
45 * the stack, and components of an unboxed tuple will be returned on
46 * the stack rather than in registers.
47 */
48 #if MACHREGS_NO_REGS == 1
49
50 /* Nothing */
51
52 #elif MACHREGS_NO_REGS == 0
53
54 /* ----------------------------------------------------------------------------
55 Caller saves and callee-saves regs.
56
57 Caller-saves regs have to be saved around C-calls made from STG
58 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
59 is designated caller-saves in that machine's C calling convention.
60
61 As it stands, the only registers that are ever marked caller saves
62 are the RX, FX, DX and USER registers; as a result, if you
63 decide to caller save a system register (e.g. SP, HP, etc), note that
64 this code path is completely untested! -- EZY
65 -------------------------------------------------------------------------- */
66
67 /* -----------------------------------------------------------------------------
68 The x86 register mapping
69
70 Ok, we've only got 6 general purpose registers, a frame pointer and a
71 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
72 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
73 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
74
75 Reg STG-Reg
76 ---------------
77 ebx Base
78 ebp Sp
79 esi R1
80 edi Hp
81
82 Leaving SpLim out of the picture.
83 -------------------------------------------------------------------------- */
84
85 #if MACHREGS_i386
86
87 #define REG(x) __asm__("%" #x)
88
89 #ifndef not_doing_dynamic_linking
90 #define REG_Base ebx
91 #endif
92 #define REG_Sp ebp
93
94 #ifndef STOLEN_X86_REGS
95 #define STOLEN_X86_REGS 4
96 #endif
97
98 #if STOLEN_X86_REGS >= 3
99 # define REG_R1 esi
100 #endif
101
102 #if STOLEN_X86_REGS >= 4
103 # define REG_Hp edi
104 #endif
105 #define REG_MachSp esp
106
107 #define REG_XMM1 xmm0
108 #define REG_XMM2 xmm1
109 #define REG_XMM3 xmm2
110 #define REG_XMM4 xmm3
111
112 #define REG_YMM1 ymm0
113 #define REG_YMM2 ymm1
114 #define REG_YMM3 ymm2
115 #define REG_YMM4 ymm3
116
117 #define REG_ZMM1 zmm0
118 #define REG_ZMM2 zmm1
119 #define REG_ZMM3 zmm2
120 #define REG_ZMM4 zmm3
121
122 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
123 #define MAX_REAL_FLOAT_REG 0
124 #define MAX_REAL_DOUBLE_REG 0
125 #define MAX_REAL_LONG_REG 0
126 #define MAX_REAL_XMM_REG 4
127 #define MAX_REAL_YMM_REG 4
128 #define MAX_REAL_ZMM_REG 4
129
130 /* -----------------------------------------------------------------------------
131 The x86-64 register mapping
132
133 %rax caller-saves, don't steal this one
134 %rbx YES
135 %rcx arg reg, caller-saves
136 %rdx arg reg, caller-saves
137 %rsi arg reg, caller-saves
138 %rdi arg reg, caller-saves
139 %rbp YES (our *prime* register)
140 %rsp (unavailable - stack pointer)
141 %r8 arg reg, caller-saves
142 %r9 arg reg, caller-saves
143 %r10 caller-saves
144 %r11 caller-saves
145 %r12 YES
146 %r13 YES
147 %r14 YES
148 %r15 YES
149
150 %xmm0-7 arg regs, caller-saves
151 %xmm8-15 caller-saves
152
153 Use the caller-saves regs for Rn, because we don't always have to
154 save those (as opposed to Sp/Hp/SpLim etc. which always have to be
155 saved).
156
157 --------------------------------------------------------------------------- */
158
159 #elif MACHREGS_x86_64
160
161 #define REG(x) __asm__("%" #x)
162
163 #define REG_Base r13
164 #define REG_Sp rbp
165 #define REG_Hp r12
166 #define REG_R1 rbx
167 #define REG_R2 r14
168 #define REG_R3 rsi
169 #define REG_R4 rdi
170 #define REG_R5 r8
171 #define REG_R6 r9
172 #define REG_SpLim r15
173 #define REG_MachSp rsp
174
175 /*
176 Map both Fn and Dn to register xmmn so that we can pass a function any
177 combination of up to six Float# or Double# arguments without touching
178 the stack. See Note [Overlapping global registers] for implications.
179 */
180
181 #define REG_F1 xmm1
182 #define REG_F2 xmm2
183 #define REG_F3 xmm3
184 #define REG_F4 xmm4
185 #define REG_F5 xmm5
186 #define REG_F6 xmm6
187
188 #define REG_D1 xmm1
189 #define REG_D2 xmm2
190 #define REG_D3 xmm3
191 #define REG_D4 xmm4
192 #define REG_D5 xmm5
193 #define REG_D6 xmm6
194
195 #define REG_XMM1 xmm1
196 #define REG_XMM2 xmm2
197 #define REG_XMM3 xmm3
198 #define REG_XMM4 xmm4
199 #define REG_XMM5 xmm5
200 #define REG_XMM6 xmm6
201
202 #define REG_YMM1 ymm1
203 #define REG_YMM2 ymm2
204 #define REG_YMM3 ymm3
205 #define REG_YMM4 ymm4
206 #define REG_YMM5 ymm5
207 #define REG_YMM6 ymm6
208
209 #define REG_ZMM1 zmm1
210 #define REG_ZMM2 zmm2
211 #define REG_ZMM3 zmm3
212 #define REG_ZMM4 zmm4
213 #define REG_ZMM5 zmm5
214 #define REG_ZMM6 zmm6
215
216 #if !defined(mingw32_HOST_OS)
217 #define CALLER_SAVES_R3
218 #define CALLER_SAVES_R4
219 #endif
220 #define CALLER_SAVES_R5
221 #define CALLER_SAVES_R6
222
223 #define CALLER_SAVES_F1
224 #define CALLER_SAVES_F2
225 #define CALLER_SAVES_F3
226 #define CALLER_SAVES_F4
227 #define CALLER_SAVES_F5
228 #if !defined(mingw32_HOST_OS)
229 #define CALLER_SAVES_F6
230 #endif
231
232 #define CALLER_SAVES_D1
233 #define CALLER_SAVES_D2
234 #define CALLER_SAVES_D3
235 #define CALLER_SAVES_D4
236 #define CALLER_SAVES_D5
237 #if !defined(mingw32_HOST_OS)
238 #define CALLER_SAVES_D6
239 #endif
240
241 #define CALLER_SAVES_XMM1
242 #define CALLER_SAVES_XMM2
243 #define CALLER_SAVES_XMM3
244 #define CALLER_SAVES_XMM4
245 #define CALLER_SAVES_XMM5
246 #if !defined(mingw32_HOST_OS)
247 #define CALLER_SAVES_XMM6
248 #endif
249
250 #define CALLER_SAVES_YMM1
251 #define CALLER_SAVES_YMM2
252 #define CALLER_SAVES_YMM3
253 #define CALLER_SAVES_YMM4
254 #define CALLER_SAVES_YMM5
255 #if !defined(mingw32_HOST_OS)
256 #define CALLER_SAVES_YMM6
257 #endif
258
259 #define CALLER_SAVES_ZMM1
260 #define CALLER_SAVES_ZMM2
261 #define CALLER_SAVES_ZMM3
262 #define CALLER_SAVES_ZMM4
263 #define CALLER_SAVES_ZMM5
264 #if !defined(mingw32_HOST_OS)
265 #define CALLER_SAVES_ZMM6
266 #endif
267
268 #define MAX_REAL_VANILLA_REG 6
269 #define MAX_REAL_FLOAT_REG 6
270 #define MAX_REAL_DOUBLE_REG 6
271 #define MAX_REAL_LONG_REG 0
272 #define MAX_REAL_XMM_REG 6
273 #define MAX_REAL_YMM_REG 6
274 #define MAX_REAL_ZMM_REG 6
275
276 /* -----------------------------------------------------------------------------
277 The PowerPC register mapping
278
279 0 system glue? (caller-save, volatile)
280 1 SP (callee-save, non-volatile)
281 2 AIX, powerpc64-linux:
282 RTOC (a strange special case)
283 darwin:
284 (caller-save, volatile)
285 powerpc32-linux:
286 reserved for use by system
287
288 3-10 args/return (caller-save, volatile)
289 11,12 system glue? (caller-save, volatile)
290 13 on 64-bit: reserved for thread state pointer
291 on 32-bit: (callee-save, non-volatile)
292 14-31 (callee-save, non-volatile)
293
294 f0 (caller-save, volatile)
295 f1-f13 args/return (caller-save, volatile)
296 f14-f31 (callee-save, non-volatile)
297
298 \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes.
299 \tr{0}--\tr{12} are caller-save registers.
300
301 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
302
303 We can do the Whole Business with callee-save registers only!
304 -------------------------------------------------------------------------- */
305
306 #elif MACHREGS_powerpc
307
308 #define REG(x) __asm__(#x)
309
310 #define REG_R1 r14
311 #define REG_R2 r15
312 #define REG_R3 r16
313 #define REG_R4 r17
314 #define REG_R5 r18
315 #define REG_R6 r19
316 #define REG_R7 r20
317 #define REG_R8 r21
318
319 #if MACHREGS_darwin
320
321 #define REG_F1 f14
322 #define REG_F2 f15
323 #define REG_F3 f16
324 #define REG_F4 f17
325
326 #define REG_D1 f18
327 #define REG_D2 f19
328
329 #else
330
331 #define REG_F1 fr14
332 #define REG_F2 fr15
333 #define REG_F3 fr16
334 #define REG_F4 fr17
335
336 #define REG_D1 fr18
337 #define REG_D2 fr19
338
339 #endif
340
341 #define REG_Sp r22
342 #define REG_SpLim r24
343
344 #define REG_Hp r25
345
346 #define REG_Base r27
347
348 /* -----------------------------------------------------------------------------
349 The Sun SPARC register mapping
350
351 !! IMPORTANT: if you change this register mapping you must also update
352 compiler/nativeGen/SPARC/Regs.hs. That file handles the
353 mapping for the NCG. This one only affects via-c code.
354
355 The SPARC register (window) story: Remember, within the Haskell
356 Threaded World, we essentially ``shut down'' the register-window
357 mechanism---the window doesn't move at all while in this World. It
358 *does* move, of course, if we call out to arbitrary~C...
359
360 The %i, %l, and %o registers (8 each) are the input, local, and
361 output registers visible in one register window. The 8 %g (global)
362 registers are visible all the time.
363
364 zero: always zero
365 scratch: volatile across C-fn calls. used by linker.
366 app: usable by application
367 system: reserved for system
368
369 alloc: allocated to in the register allocator, intra-closure only
370
371 GHC usage v8 ABI v9 ABI
372 Global
373 %g0 zero zero zero
374 %g1 alloc scratch scrach
375 %g2 alloc app app
376 %g3 alloc app app
377 %g4 alloc app scratch
378 %g5 system scratch
379 %g6 system system
380 %g7 system system
381
382 Output: can be zapped by callee
383 %o0-o5 alloc caller saves
384 %o6 C stack ptr
385 %o7 C ret addr
386
387 Local: maintained by register windowing mechanism
388 %l0 alloc
389 %l1 R1
390 %l2 R2
391 %l3 R3
392 %l4 R4
393 %l5 R5
394 %l6 alloc
395 %l7 alloc
396
397 Input
398 %i0 Sp
399 %i1 Base
400 %i2 SpLim
401 %i3 Hp
402 %i4 alloc
403 %i5 R6
404 %i6 C frame ptr
405 %i7 C ret addr
406
407 The paired nature of the floating point registers causes complications for
408 the native code generator. For convenience, we pretend that the first 22
409 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
410 float (single) regs. The NCG acts accordingly. That means that the
411 following FP assignment is rather fragile, and should only be changed
412 with extreme care. The current scheme is:
413
414 %f0 /%f1 FP return from C
415 %f2 /%f3 D1
416 %f4 /%f5 D2
417 %f6 /%f7 ncg double spill tmp #1
418 %f8 /%f9 ncg double spill tmp #2
419 %f10/%f11 allocatable
420 %f12/%f13 allocatable
421 %f14/%f15 allocatable
422 %f16/%f17 allocatable
423 %f18/%f19 allocatable
424 %f20/%f21 allocatable
425
426 %f22 F1
427 %f23 F2
428 %f24 F3
429 %f25 F4
430 %f26 ncg single spill tmp #1
431 %f27 ncg single spill tmp #2
432 %f28 allocatable
433 %f29 allocatable
434 %f30 allocatable
435 %f31 allocatable
436
437 -------------------------------------------------------------------------- */
438
439 #elif MACHREGS_sparc
440
441 #define REG(x) __asm__("%" #x)
442
443 #define CALLER_SAVES_USER
444
445 #define CALLER_SAVES_F1
446 #define CALLER_SAVES_F2
447 #define CALLER_SAVES_F3
448 #define CALLER_SAVES_F4
449 #define CALLER_SAVES_D1
450 #define CALLER_SAVES_D2
451
452 #define REG_R1 l1
453 #define REG_R2 l2
454 #define REG_R3 l3
455 #define REG_R4 l4
456 #define REG_R5 l5
457 #define REG_R6 i5
458
459 #define REG_F1 f22
460 #define REG_F2 f23
461 #define REG_F3 f24
462 #define REG_F4 f25
463
464 /* for each of the double arg regs,
465 Dn_2 is the high half. */
466
467 #define REG_D1 f2
468 #define REG_D1_2 f3
469
470 #define REG_D2 f4
471 #define REG_D2_2 f5
472
473 #define REG_Sp i0
474 #define REG_SpLim i2
475
476 #define REG_Hp i3
477
478 #define REG_Base i1
479
480 #define NCG_FirstFloatReg f22
481
482 /* -----------------------------------------------------------------------------
483 The ARM EABI register mapping
484
485 Here we consider ARM mode (i.e. 32bit isns)
486 and also CPU with full VFPv3 implementation
487
488 ARM registers (see Chapter 5.1 in ARM IHI 0042D)
489
490 r15 PC The Program Counter.
491 r14 LR The Link Register.
492 r13 SP The Stack Pointer.
493 r12 IP The Intra-Procedure-call scratch register.
494 r11 v8 Variable-register 8.
495 r10 v7 Variable-register 7.
496 r9 v6/SB/TR Platform register. The meaning of this register is
497 defined by the platform standard.
498 r8 v5 Variable-register 5.
499 r7 v4 Variable register 4.
500 r6 v3 Variable register 3.
501 r5 v2 Variable register 2.
502 r4 v1 Variable register 1.
503 r3 a4 Argument / scratch register 4.
504 r2 a3 Argument / scratch register 3.
505 r1 a2 Argument / result / scratch register 2.
506 r0 a1 Argument / result / scratch register 1.
507
508 VFPv2/VFPv3/NEON registers
509 s0-s15/d0-d7/q0-q3 Argument / result/ scratch registers
510 s16-s31/d8-d15/q4-q7 callee-saved registers (must be preserved across
511 subrutine calls)
512
513 VFPv3/NEON registers (added to the VFPv2 registers set)
514 d16-d31/q8-q15 Argument / result/ scratch registers
515 ----------------------------------------------------------------------------- */
516
517 #elif MACHREGS_arm
518
519 #define REG(x) __asm__(#x)
520
521 #define REG_Base r4
522 #define REG_Sp r5
523 #define REG_Hp r6
524 #define REG_R1 r7
525 #define REG_R2 r8
526 #define REG_R3 r9
527 #define REG_R4 r10
528 #define REG_SpLim r11
529
530 #if !defined(arm_HOST_ARCH_PRE_ARMv6)
531 /* d8 */
532 #define REG_F1 s16
533 #define REG_F2 s17
534 /* d9 */
535 #define REG_F3 s18
536 #define REG_F4 s19
537
538 #define REG_D1 d10
539 #define REG_D2 d11
540 #endif
541
542 /* -----------------------------------------------------------------------------
543 The ARMv8/AArch64 ABI register mapping
544
545 The AArch64 provides 31 64-bit general purpose registers
546 and 32 128-bit SIMD/floating point registers.
547
548 General purpose registers (see Chapter 5.1.1 in ARM IHI 0055B)
549
550 Register | Special | Role in the procedure call standard
551 ---------+---------+------------------------------------
552 SP | | The Stack Pointer
553 r30 | LR | The Link Register
554 r29 | FP | The Frame Pointer
555 r19-r28 | | Callee-saved registers
556 r18 | | The Platform Register, if needed;
557 | | or temporary register
558 r17 | IP1 | The second intra-procedure-call temporary register
559 r16 | IP0 | The first intra-procedure-call scratch register
560 r9-r15 | | Temporary registers
561 r8 | | Indirect result location register
562 r0-r7 | | Parameter/result registers
563
564
565 FPU/SIMD registers
566
567 s/d/q/v0-v7 Argument / result/ scratch registers
568 s/d/q/v8-v15 callee-saved registers (must be preserved across subrutine calls,
569 but only bottom 64-bit value needs to be preserved)
570 s/d/q/v16-v31 temporary registers
571
572 ----------------------------------------------------------------------------- */
573
574 #elif MACHREGS_aarch64
575
576 #define REG(x) __asm__(#x)
577
578 #define REG_Base r19
579 #define REG_Sp r20
580 #define REG_Hp r21
581 #define REG_R1 r22
582 #define REG_R2 r23
583 #define REG_R3 r24
584 #define REG_R4 r25
585 #define REG_R5 r26
586 #define REG_R6 r27
587 #define REG_SpLim r28
588
589 #define REG_F1 s8
590 #define REG_F2 s9
591 #define REG_F3 s10
592 #define REG_F4 s11
593
594 #define REG_D1 d12
595 #define REG_D2 d13
596 #define REG_D3 d14
597 #define REG_D4 d15
598
599 #else
600
601 #error Cannot find platform to give register info for
602
603 #endif
604
605 #else
606
607 #error Bad MACHREGS_NO_REGS value
608
609 #endif
610
611 /* -----------------------------------------------------------------------------
612 * These constants define how many stg registers will be used for
613 * passing arguments (and results, in the case of an unboxed-tuple
614 * return).
615 *
616 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
617 * highest STG register to occupy a real machine register, otherwise
618 * the calling conventions will needlessly shuffle data between the
619 * stack and memory-resident STG registers. We might occasionally
620 * set these macros to other values for testing, though.
621 *
622 * Registers above these values might still be used, for instance to
623 * communicate with PrimOps and RTS functions.
624 */
625
626 #ifndef MAX_REAL_VANILLA_REG
627 # if defined(REG_R10)
628 # define MAX_REAL_VANILLA_REG 10
629 # elif defined(REG_R9)
630 # define MAX_REAL_VANILLA_REG 9
631 # elif defined(REG_R8)
632 # define MAX_REAL_VANILLA_REG 8
633 # elif defined(REG_R7)
634 # define MAX_REAL_VANILLA_REG 7
635 # elif defined(REG_R6)
636 # define MAX_REAL_VANILLA_REG 6
637 # elif defined(REG_R5)
638 # define MAX_REAL_VANILLA_REG 5
639 # elif defined(REG_R4)
640 # define MAX_REAL_VANILLA_REG 4
641 # elif defined(REG_R3)
642 # define MAX_REAL_VANILLA_REG 3
643 # elif defined(REG_R2)
644 # define MAX_REAL_VANILLA_REG 2
645 # elif defined(REG_R1)
646 # define MAX_REAL_VANILLA_REG 1
647 # else
648 # define MAX_REAL_VANILLA_REG 0
649 # endif
650 #endif
651
652 #ifndef MAX_REAL_FLOAT_REG
653 # if defined(REG_F4)
654 # define MAX_REAL_FLOAT_REG 4
655 # elif defined(REG_F3)
656 # define MAX_REAL_FLOAT_REG 3
657 # elif defined(REG_F2)
658 # define MAX_REAL_FLOAT_REG 2
659 # elif defined(REG_F1)
660 # define MAX_REAL_FLOAT_REG 1
661 # else
662 # define MAX_REAL_FLOAT_REG 0
663 # endif
664 #endif
665
666 #ifndef MAX_REAL_DOUBLE_REG
667 # if defined(REG_D2)
668 # define MAX_REAL_DOUBLE_REG 2
669 # elif defined(REG_D1)
670 # define MAX_REAL_DOUBLE_REG 1
671 # else
672 # define MAX_REAL_DOUBLE_REG 0
673 # endif
674 #endif
675
676 #ifndef MAX_REAL_LONG_REG
677 # if defined(REG_L1)
678 # define MAX_REAL_LONG_REG 1
679 # else
680 # define MAX_REAL_LONG_REG 0
681 # endif
682 #endif
683
684 #ifndef MAX_REAL_XMM_REG
685 # if defined(REG_XMM6)
686 # define MAX_REAL_XMM_REG 6
687 # elif defined(REG_XMM5)
688 # define MAX_REAL_XMM_REG 5
689 # elif defined(REG_XMM4)
690 # define MAX_REAL_XMM_REG 4
691 # elif defined(REG_XMM3)
692 # define MAX_REAL_XMM_REG 3
693 # elif defined(REG_XMM2)
694 # define MAX_REAL_XMM_REG 2
695 # elif defined(REG_XMM1)
696 # define MAX_REAL_XMM_REG 1
697 # else
698 # define MAX_REAL_XMM_REG 0
699 # endif
700 #endif
701
702 /* define NO_ARG_REGS if we have no argument registers at all (we can
703 * optimise certain code paths using this predicate).
704 */
705 #if MAX_REAL_VANILLA_REG < 2
706 #define NO_ARG_REGS
707 #else
708 #undef NO_ARG_REGS
709 #endif
710
711 #endif /* MACHREGS_H */